公开(公告)号：KR1020030048685A

公开(公告)日：2003-06-25

申请号：KR1020010078666

申请日：2001-12-12

Applicant: 한국전자통신연구원

Inventor： 이대우 ,  김종대

IPC: H01L29/78

CPC classification number: H01L29/402 ,  H01L29/66659 ,  H01L29/7835

Abstract: PURPOSE: An EDMOSFET(Extended Drain Metal Oxide Semiconductor Field Effect Transistor) having a source field plate and a method for manufacturing the same are provided to be capable of showing field plate effect enough while using the transistor in the middle voltage range by forming the first interlayer dielectric relatively having a thin thickness between the source field plate and a gate conductive layer. CONSTITUTION: The first conductive type well region(202), the second conductive type drift region(204), and the second conductive type high concentration drain region(210) are sequentially formed on the first conductive type semiconductor substrate(200). The second conductive type high concentration source region(206) is spaced apart from the drift region. A gate isolating layer(212) is located between the drift and source region. A gate conductive layer(214), the first interlayer dielectric(215), and a source field plate(224) are sequentially formed on the gate isolating layer. The second interlayer dielectric(216), a source electrode(222), and a drain electrode(220) are formed on the resultant structure. Preferably, the first interlayer dielectric has a thickness of 300-600 angstrom.

Abstract translation: 目的：提供一种具有源场板的EDMOSFET（扩展型漏极金属氧化物半导体场效应晶体管）及其制造方法，能够通过形成第一 层间电介质在源极场板和栅极导电层之间相对地具有薄的厚度。 构成：第一导电型阱区（202），第二导电型漂移区（204）和第二导电型高浓度漏极区域（210）依次形成在第一导电型半导体衬底（200）上。 第二导电型高浓度源区域（206）与漂移区域间隔开。 栅极隔离层（212）位于漂移源区域和源极区域之间。 在栅极绝缘层上依次形成栅极导电层（214），第一层间电介质（215）和源极场板（224）。 在所得结构上形成第二层间电介质（216），源电极（222）和漏电极（220）。 优选地，第一层间电介质的厚度为300-600埃。

公开(公告)号：KR1020030042654A

公开(公告)日：2003-06-02

申请号：KR1020010073392

申请日：2001-11-23

Applicant: 한국전자통신연구원

Inventor： 이대우 ,  노태문 ,  구진근 ,  김종대 ,  양일석 ,  박일용

IPC: H01L27/06

Abstract: PURPOSE: A method for fabricating a Bipolar-CMOS-DMOS(BCD) device is provided to fabricate a BCD device that has voltage tolerance of 20-30 volt and 60-90 volt and gate oxide layers of different thicknesses by using a CMOS device process of a submicron class. CONSTITUTION: Only a drift region is formed under a drain region of a lateral double diffused MOS(LDMOS) device of 20-30 volt class while a drift region is formed under a drain region of 60-90 volt class so that a well region is formed to improve voltage tolerance and an on-resistance characteristic. A gate oxide layer of an nLDMOS device is made thin while a gate oxide layer of a pLDMOS device is made thick so that a gate apply voltage is increased to improve driving capability. A device occupying area is reduced by isolating devices while using a trench. A drift region of a DMOS device is formed to simplify a process by using a mask for forming the base of a bipolar device.

Abstract translation: 目的：提供一种用于制造双极CMOS-DMOS（BCD）器件的方法，以通过使用CMOS器件工艺来制造电压容差为20-30伏和60-90伏特的不同厚度的栅极氧化物层的BCD器件 的亚微米级。 构成：在20-30伏等级的横向双扩散MOS（LDMOS）器件的漏极区域下方仅形成漂移区域，而在60-90伏特级别的漏极区域形成漂移区域，使得阱区域为 形成以提高耐压性和导通电阻特性。 使nLDMOS器件的栅极氧化层变薄，同时使pLDMOS器件的栅极氧化物层变厚，从而增加栅极施加电压以改善驱动能力。 使用沟槽时，通过隔离装置来减少装置占用面积。 形成DMOS器件的漂移区域，以通过使用用于形成双极器件的基极的掩模来简化工艺。

公开(公告)号：KR1020020054109A

公开(公告)日：2002-07-06

申请号：KR1020000082804

申请日：2000-12-27

Applicant: 한국전자통신연구원

Inventor： 이대우 ,  노태문 ,  구진근 ,  김종대 ,  조경익

IPC: H01L27/092

Abstract: PURPOSE: A power device having a trench drain field plate is provided to control extension of space charges at the edge of a gate by including a trench structure in a drift region, and to obtain a breakdown voltage and a low on-resistance by improving reduced surface field(RESURF) effect. CONSTITUTION: A buried layer of the first conductivity type and the epi layer of the second conductivity type are formed on a silicon substrate. A diffusion layer of the first conductivity type as a channel portion is formed on the buried layer. The drift region of the second conductivity type is partially formed on the epi layer. A gate insulation layer is partially formed in the diffusion layer and the drift region. A part of the drift region is formed of a trench structure so that the edge of the gate partially extends in the trench. A drain field plate is formed on an insulation layer having a thickness different from that of the gate insulation layer, connected from the inside of the trench to a drain.

Abstract translation: 目的：提供一种具有沟槽漏极场板的功率器件，以通过在漂移区域中包括沟槽结构来控制栅极边缘处的空间电荷的扩展，并通过改善降低电压来获得击穿电压和低导通电阻 表面场（RESURF）效应。 构成：在硅衬底上形成第一导电类型的掩埋层和第二导电类型的外延层。 作为沟道部分的第一导电类型的扩散层形成在掩埋层上。 第二导电类型的漂移区部分地形成在外延层上。 栅极绝缘层部分地形成在扩散层和漂移区域中。 漂移区的一部分由沟槽结构形成，使得栅极的边缘在沟槽中部分地延伸。 漏极场板形成在绝缘层上，其绝缘层的厚度不同于从沟槽的内部连接到漏极的栅极绝缘层的厚度。

公开(公告)号：KR1020010062967A

公开(公告)日：2001-07-09

申请号：KR1019990059752

申请日：1999-12-21

Applicant: 한국전자통신연구원

Inventor： 노태문 ,  이대우 ,  남기수 ,  김종대 ,  김상기 ,  구진근

IPC: H01L27/088

Abstract: PURPOSE: A high speed power transistor and a fabrication method thereof are provided to reduce the resistance of a trench gate electrode and thus to increase an operation speed of the device by reducing a transfer delay time of an electrical signal by the reduction of the resistance. CONSTITUTION: A gate is formed by stacking a polysilicon and a metal in a trench. A lightly doped N-type silicon epi layer(2) is grown on a heavily doped N-type silicon substrate(1). After growing a thin oxide on the epi layer, an N-type impurity ion is implanted to form a body(3) and is annealed. A nitride film pattern is formed on the oxide and a heavily doped N-type impurity ion is implanted and a well(4) is formed by a high temperature annealing as growing the oxide on the revealed part. And a source junction(5) is formed by implanting a heavily doped P-type impurity ion. After removing the oxide and forming an insulation film(11), a trench is formed by dry-etching the insulation film and the source junction and the body and a part of the epi layer on the gate region. After forming a gate oxide(12) in the trench, a doped polysilicon(14) and a metal(15) are stacked. After etching a part of the polysilicon and the metal, an interlayer insulation film(13) is deposited. And, an electrode contacted to each of the source junction and the metal is formed by etching the interlayer insulation film selectively, and a drain is formed under the silicon substrate.

Abstract translation: 目的：提供一种高速功率晶体管及其制造方法，以减小沟槽栅电极的电阻，从而通过降低电阻降低电信号的传输延迟时间来提高器件的工作速度。 构成：通过在沟槽中堆叠多晶硅和金属形成栅极。 在重掺杂的N型硅衬底（1）上生长轻掺杂的N型硅外延层（2）。 在epi层上生长薄氧化物后，注入N型杂质离子以形成体（3）并进行退火。 在氧化物上形成氮化物膜图案，并且注入重掺杂的N型杂质离子，并且通过在显露部分上生长氧化物的高温退火形成阱（4）。 并且通过注入重掺杂的P型杂质离子形成源极结（5）。 在去除氧化物并形成绝缘膜（11）之后，通过干蚀刻栅极区上的绝缘膜和源极结以及主体和外延层的一部分来形成沟槽。 在沟槽中形成栅极氧化物（12）之后，堆叠掺杂多晶硅（14）和金属（15）。 在蚀刻多晶硅和金属的一部分之后，沉积层间绝缘膜（13）。 并且，通过选择性地蚀刻层间绝缘膜来形成与源极结和金属中的每一个接触的电极，并且在硅衬底下方形成漏极。

公开(公告)号：KR1020010057754A

公开(公告)日：2001-07-05

申请号：KR1019990061152

申请日：1999-12-23

Applicant: 한국전자통신연구원

Inventor： 이대우 ,  노태문 ,  구진근 ,  조경익

IPC: H01L27/092

Abstract: PURPOSE: A power device having a trench drain structure is provided to improve reliability of a high voltage power device, by mitigating a current crowding effect in a high electric field region so that a high breakdown voltage is maintained and current is easily controlled. CONSTITUTION: The second conductive drift region is formed in the first conductive epitaxial layer on a semiconductor substrate. The first conductive well region is formed in the epitaxial layer, surrounding the second conductive drift region. The interface between the second conductive drift region and the first conductive well region has a saw-tooth shape. The second conductive source region is formed in the first conductive well region. The second conductive drain region is formed in the second conductive drift region. The interface between the second conductive drift region and the second conductor drain region has a saw-tooth shape. A part of the second conductive drain region has a trench structure of a saw-tooth shape. A gate is formed between the second conductive source region and the second conductive drain.

Abstract translation: 目的：提供具有沟槽漏极结构的功率器件，以通过减轻高电场区域中的电流拥挤效应来提高高压功率器件的可靠性，从而保持高的击穿电压并容易地控制电流。 构成：第二导电漂移区形成在半导体衬底上的第一导电外延层中。 第一导电阱区形成在外延层中，围绕第二导电漂移区。 第二导电漂移区和第一导电阱区之间的界面具有锯齿形状。 第二导电源区形成在第一导电阱区中。 第二导电漏极区域形成在第二导电漂移区域中。 第二导电漂移区域和第二导体漏极区域之间的界面具有锯齿形状。 第二导电漏极区域的一部分具有锯齿形状的沟槽结构。 在第二导电源区域和第二导电漏极之间形成栅极。

公开(公告)号：KR100275494B1

公开(公告)日：2001-01-15

申请号：KR1019980016540

申请日：1998-05-08

Applicant: 한국전자통신연구원

Inventor： 이대우 ,  노태문 ,  구진근 ,  남기수

IPC: H01L29/78

Abstract: PURPOSE: A race-tack type current-controlled power device and a fabricating method thereof are provided to increase a breakdown voltage by reducing a field enhancement effect. CONSTITUTION: A p- epitaxial layer(2) is formed on a p type silicon substrate(1). A p well(3) as a channel region and an n drift region(4) are formed by performing a mask process, a dopant implantation process, and a high thermal process. A buffer oxide layer and a nitride layer are formed by performing a LOCOS(LOCal Oxidation of Silicon) process. A photo-resist layer is applied on a whole surface of the structure. A photo-resist layer pattern is defined by performing a mask process using an isolation mask. An oxide barrier pattern is formed by etching the nitride layer and the buffer oxide layer. The photo-resist layer pattern is removed. A field oxide layer(8) is grown thereon. The nitride layer and the buffer oxide layer are removed. A gate oxide layer and a polysilicon layer(10) are formed on the channel region. An n+ source(11a), a p+ source contact layer(12), and an n+ drain(11b) are formed by performing an ion implantation process. A source electrode(14), a drain electrode(15), and a gate electrode are formed by forming and etching a metal layer on the whole surface.

Abstract translation: 目的：提供一种耐磨型电流控制功率器件及其制造方法，以通过减小场增强效应来增加击穿电压。 构成：在p型硅衬底（1）上形成p-外延层（2）。 通过执行掩模处理，掺杂剂注入工艺和高热处理来形成作为沟道区和n漂移区（4）的p阱（3）。 通过执行LOCOS（硅的局部氧化）工艺来形成缓冲氧化物层和氮化物层。 在结构的整个表面上施加光刻胶层。 通过使用隔离掩模执行掩模处理来定义光刻胶层图案。 通过蚀刻氮化物层和缓冲氧化物层形成氧化物阻挡图案。 除去光致抗蚀剂图案。 在其上生长场氧化物层（8）。 去除氮化物层和缓冲氧化物层。 在沟道区上形成栅氧化层和多晶硅层（10）。 通过进行离子注入工艺来形成n +源极（11a），p +源极接触层（12）和n +漏极（11b）。 通过在整个表面上形成和蚀刻金属层来形成源电极（14），漏电极（15）和栅电极。

公开(公告)号：KR1020000032754A

公开(公告)日：2000-06-15

申请号：KR1019980049309

申请日：1998-11-17

Applicant: 한국전자통신연구원

Inventor： 남기수 ,  노태문 ,  김상기 ,  김종대 ,  이대우 ,  구진근 ,  김대용

IPC: H01L29/78

Abstract: PURPOSE: A power device having vertical trench gates and a thick oxide layer on drift region is provided to obtain high breakdown voltage and low ON-resistance. CONSTITUTION: A high voltage power device used for a step motor, an automobile, and a plate display drive IC is fabricated. Source regions(28) are formed in both sides of a silicon substrate(20) having p-wells(25) therein, and a drain region(26) is formed in a mmiddle of the substrate(20). A trench(29) is then formed between the source and drain regions(28,26). A first thick field oxide layer(35) is formed on both a bottom surface and a side wall of the trench(29) in the drift region, and on the source and drain regions(28,26). A gate layer(37) is formed in the trench(29) surrounded by the first field oxide layer(35), and an oxide layer(36') is further formed on the gate layer(37). Moreover, a second field oxide layer(38) is formed on the oxide layers(35,36'). Source electrodes(39) and a drain electrode(40) are formed in contact holes of the first and second field oxide layer(35,38). Particularly, in the trench(29), the bottom gate oxide layer and the side wall gate oxide layer toward the drift region are thicker than the other side wall gate oxide layer toward a channel region.

Abstract translation: 目的：提供具有垂直沟槽栅极和漂移区上厚厚氧化层的功率器件，以获得高击穿电压和低导通电阻。 构成：制造用于步进电机，汽车和板显示驱动IC的高压电力装置。 源极区（28）形成在其中具有p阱（25）的硅衬底（20）的两侧，并且在衬底（20）的mm中形成漏极区（26）。 然后在源区和漏区（28,26）之间形成沟槽（29）。 第一厚氧化物层（35）形成在漂移区域中的沟槽（29）的底表面和侧壁上以及源极和漏极区域（28,26）上。 在由第一场氧化物层（35）围绕的沟槽（29）中形成栅极层（37），并且在栅极层（37）上进一步形成氧化物层（36'）。 此外，在氧化物层（35,36'）上形成第二场氧化物层（38）。 源电极（39）和漏电极（40）形成在第一和第二场氧化物层（35,38）的接触孔中。 特别地，在沟槽（29）中，底栅氧化层和侧壁栅氧化层朝向漂移区比另一侧壁栅极氧化物层朝向沟道区域厚。

公开(公告)号：KR1020000031962A

公开(公告)日：2000-06-05

申请号：KR1019980048234

申请日：1998-11-11

Applicant: 한국전자통신연구원

Inventor： 남기수 ,  노태문 ,  김상기 ,  김종대 ,  이대우 ,  구진근 ,  김대용

IPC: H01L27/108

Abstract: PURPOSE: A high voltage electric power device is provided to be used for a stepped motor, an automobile, and an integrated circuit for driving flat board display by having the structure of a trench gate type containing a high yield voltage and a low ON-resistance value. CONSTITUTION: Wells(3) are formed on both upper parts of a device area in a semiconductor substrate(1), and a trench structure is formed to have two trench grooves between wells. Thus, a gate oxidation film is formed in the trench groove. Moreover, a gate oxidation film is formed to have the side wall of a channel area, which is thicker than the side wall of a drift area. Then, a polycrystalline silicon thin film is formed for being surrounded by the gate oxidation film as a gate electrode(12). Herein, a source area(17) containing n+ and p+ ions in the well area of one side is formed on an upper part of the well, and the source area containing n+ and p+ ions is formed at the well area of the other side. A drain area(15) having the n+ ion is formed on the upper surface of a column in the trench structure, and a field oxide film is formed on the upper part of the drain area. Moreover, a contact hole is formed in both source areas to form the source electrode and a drain electrode(18).

Abstract translation: 目的：提供一种高压电力装置，用于阶梯式电动机，汽车和用于驱动平板显示器的集成电路，其具有包含高屈服电压和低导通电阻的沟槽栅型结构 值。 构成：在半导体衬底（1）中的器件区域的两个上部形成有阱（3），并且形成沟槽结构以在阱之间具有两个沟槽。 因此，在沟槽中形成栅极氧化膜。 此外，形成栅极氧化膜以具有比漂移区域的侧壁更厚的沟道区域的侧壁。 然后，形成由栅极氧化膜作为栅电极（12）包围的多晶硅薄膜。 这里，在井的上部形成在一侧的阱区域中含有n +和p +离子的源极区域（17），在另一侧的阱区域形成有含有n +和p +离子的源极区域。 在沟槽结构的列的上表面上形成具有n +离子的漏极区域（15），并且在漏极区域的上部形成场氧化膜。 此外，在两个源极区域中形成接触孔以形成源电极和漏电极（18）。

公开(公告)号：KR1019990053178A

公开(公告)日：1999-07-15

申请号：KR1019970072769

申请日：1997-12-23

Applicant: 한국전자통신연구원

Inventor： 노태문 ,  구용서 ,  이대우 ,  구진근 ,  남기수

IPC: H01L21/33

Abstract: 본 발명은 스마트 전력 집적회로(Smart Power IC)에 관한 것으로서, 특히 고속 하드 디스크 드라이버(HDD)등 고성능 컴퓨터 시스템의 핵심기술인 고속-고내압-고신뢰성 특성에 부합하기위한 최적화 바이폴라-래터럴파워 모스페트(Bi-LDMOSFET) 에 관한 것이다.
정보통신기술의 비약적인 발전추세에 따라 디지털 이동통신, 가전제품을 비롯한 전자산업, 고성능 컴퓨터 시스템(고속 HDD 드라이버), 자동차의 전자제어 시스템 등의 핵심 IC 기술로서, 초고속-고내압 특성이 요구되고 있다.
따라서 본 발명은 초고속, 고주파, 고신뢰성, 저전력 특성을 만족시키는 SOI Bi-LDMOSFET의 제조 방법을 제시하기로 한다.

公开(公告)号：KR1019990032178A

公开(公告)日：1999-05-06

申请号：KR1019970053153

申请日：1997-10-16

Applicant: 한국전자통신연구원

Inventor： 구진근 ,  남기수 ,  구용서 ,  이대우 ,  노태문

IPC: H01L27/06

Abstract: 본 발명은 고속, 고내압 BCD Power IC 소자의 제조 방법에 관한 것으로서, 3중 매몰층 및 에피층 형성공정, LDPMOS 소자의 드리프트 및 이중 웰 형성 공정, 트랜치 소자 격리 및 싱크(Sink) 확산 공정, HV-NMOS/HV-PMOS/LDNMOS의 드리프트 영역 및 HV-pnp 베이스 영역 동시형성 공정, HS-PSA 베이스 형성 및 문턱전압 조절 공정, 게이트, 다결정실리콘 에미터 전극형성 및 LDD 공정, 측면 산화막 형성 및 소스-드레인 영역형성 공정, 보호산화막 도포 및 금속전극 형성 공정을 수행하여 고주파/고내압/고집적화/고신뢰성화된 구조를 고안함으로써, 휴대폰 및 고속 HDD IC를 비롯한 고품위 정보통신 시스템, 가전제품, 자동차 전자제어 장치 등에 다양하게 사용할 수 있는 효과가 있다.