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公开(公告)号：KR102198639B1
公开(公告)日：2021-01-06
申请号：KR1020160167031
申请日：2016-12-08
Applicant: 한국전자통신연구원 , 단국대학교 산학협력단
IPC: H01L27/02
Abstract: 본발명은정전기방전보호소자및 이를포함하는전자디바이스에관한것이다. 본발명의실시예에따른정전기방전보호소자및 이를포함하는전자디바이스는제1 P웰, 제2 P웰, N웰, N+ 브릿지영역, P+ 브릿지영역, 제1 N+ 영역, 제1 P+ 영역, 제2 N+ 영역, 제2 P+ 영역및 게이트를포함한다. N웰은제1 P웰및 제2 P웰사이에배치된다. N+ 브릿지영역은제2 P웰및 N웰의접합영역에형성된다. P+ 브릿지영역은제1 P웰및 N웰의접합영역에형성된다. 제1 N+ 영역및 제1 P+ 영역은제1 P웰에형성되고, 애노드단자에연결된다. 제2 N+ 영역및 제2 P+ 영역은제2 P웰에형성되고, 캐소드단자에연결된다. 게이트는 N+ 브릿지영역및 제2 N+ 영역사이의제2 P웰상에배치된다. 본발명의실시예에따른정전기방전보호소자는트리거전압을낮추고, 전류구동능력을향상시킨다.
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公开(公告)号：KR101140347B1
公开(公告)日：2012-05-03
申请号：KR1020080115049
申请日：2008-11-19
Applicant: 한국전자통신연구원
CPC classification number: H02M1/08 , H02M2001/0032 , Y02B70/16
Abstract: 본 발명에 따른 스위칭 회로는 동적 문턱 전압을 갖는 DT-CMOS(Dynamic Threshold - Complementary Metal Oxide Semiconductor) 트랜지스터를 스위칭 소자로 이용하여 정상 모드시에는 낮은 문턱 전압을 유지하도록 하여 전류 구동력을 향상시키면서 도통 손실을 감소시키고, 대기 모드시에는 높은 문턱전압을 유지하도록 하여 전력 소모를 최소화할 수 있다. 따라서, 본 발명에 따른 스위칭 회로를 DC-DC 변환기에 적용하면, 정상 모드시 도통 손실을 줄여 전력 변환 효율을 더 높일 수 있고 대기 모드시 전력 소모를 최소화할 수 있으므로, 휴대기기의 배터리 사용시간을 최대화할 수 있어 점차 소형화되어가는 휴대기기 전원 장치에 유용하게 사용할 수 있는 효과가 있다.
동적 문턱 전압(Dynamic Threshold voltage), DT-CMOS, 스위칭 소자(Switching device), DC-DC 변환기(DC-DC Converter), 펄스 폭 변조(Pulse Width Modulation), 온 저항(On-resistance), 누설전류(Leakage current)-
公开(公告)号：KR1019950007348B1
公开(公告)日：1995-07-10
申请号：KR1019920009982
申请日：1992-06-09
Applicant: 한국전자통신연구원 , 재단법인한국전자통신연구소 , 주식회사 케이티
IPC: H01L29/70
Abstract: an emitter(2) of n+ buried layer(2) formed on a substrate(1); a polysilicon layer(3), an n- epitaxial layer(4), an oxide layer(5), a nitride layer(6) and a low temp. depositing oxide layer grown on the n+ buried layer(2) in turn; an isolation oxide layer(8) grown to be formed on a trench formed by etching the respective growth layer; a field oxide layer(9) formed by selectively growing an active region to position the interface of the oxide layer and the nitride layer at the n+ buried layer(2); a N+ polycrystal silicon electrode and a collector formed by selectively etching the grown layers; a base contact region formed by selective etching of a side wall nitried layer(15); a base electrode formed by growing the P+ polycrystal silicon layer(18); and a metal wiring formed by covering the contact opening with aluminium. The transistor has the increased voltage and the high switching speed in IIL circuit.
Abstract translation: 在衬底（1）上形成的n +掩埋层（2）的发射极（2）; 多晶硅层（3），n外延层（4），氧化物层（5），氮化物层（6）和低温 依次沉积在n +掩埋层（2）上生长的氧化物层; 生长在通过蚀刻各个生长层形成的沟槽上的隔离氧化物层（8）; 通过选择性地生长活性区以在n +掩埋层（2）处定位氧化物层和氮化物层的界面而形成的场氧化物层（9）; 通过选择性蚀刻生长层形成的N +多晶硅电极和集电体; 通过选择性蚀刻侧壁三层（15）形成的基底接触区域; 通过生长P +多晶硅层（18）而形成的基极; 以及通过用铝覆盖接触开口而形成的金属布线。 晶体管在IIL电路中具有增加的电压和高开关速度。
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公开(公告)号：KR1019950001147B1
公开(公告)日：1995-02-11
申请号：KR1019910021081
申请日：1991-11-25
IPC: H01L29/70
Abstract: The method includes the steps of sequentially forming a poly-Si film (1), an oxide film (2), a nitride film (3) and a poly-Si film (4) on the substrate; growing and etching an oxide film (6) to define a device size; forming a trench isolation region (7) and poly-Si electrodes (8,9,10), depositing and etching an LPCVD oxide film thereon to expose the poly-Si films (4,8) to form a trench isolation oxide film (12) to remove the film (4) to form an unactive base electrode (25) with boron doping, growing an oxide film (13) on the electrode (25); removing a nitride film (3) to form diffusion layers (14,15,16,17), and forming a self aligned silicide layer (18) and metallic wirings on the electrode (25,26,27); thereby reducing the parasitic resistance component.
Abstract translation: 该方法包括在基板上依次形成多晶硅膜（1），氧化膜（2），氮化物膜（3）和多晶硅膜（4）的步骤; 生长和蚀刻氧化膜（6）以限定器件尺寸; 形成沟槽隔离区域（7）和多晶硅电极（8,9,10），在其上沉积和蚀刻其上的LPCVD氧化膜以暴露多晶硅膜（4,8）以形成沟槽隔离氧化膜（12 ）以去除所述膜（4）以形成具有硼掺杂的非活性基极（25），在所述电极（25）上生长氧化物膜（13）; 去除氮化物膜（3）以形成扩散层（14,15,16,17），以及在所述电极（25,26,27）上形成自对准硅化物层（18）和金属布线; 从而降低寄生电阻分量。
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Patent Agency Ranking
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公开(公告)号：KR1019890003827B1
公开(公告)日：1989-10-05
申请号：KR1019870008119
申请日：1987-07-25
IPC: H01L27/06
CPC classification number: H01L21/8249 , Y10S148/011
Abstract: The BiCMOS means a combined semiconductor with high speed Bipolar and large scale CMOS. The manufacturing process of BiCMOS involves: (a) forming p-well after the growth of epitaxy layer on n+ region formed on p-type substrate; (b) depositing the nitride film on the oxide film, and isolating the p+ junction; (c) forming base and collector of bipolar transistor by implanting impurities after growth of CMOS gate oxide; (d) forming a gate of CMOS and emitter of bipolar transistor after depositing oxide film on the n+ layer formed by impurities; (e) forming source and drain of PMOS, NMOS; (F) thermal oxidising or soarce and drain of CMOS, and Aluminium metalization.
Abstract translation: BiCMOS是指具有高速双极和大规模CMOS的组合半导体。 BiCMOS的制造过程包括：（a）在p型衬底上形成的n +区上生长外延层后形成p阱; （b）在氧化膜上沉积氮化物膜，并隔离p +结; （c）通过在CMOS栅极氧化物生长之后注入杂质形成双极晶体管的基极和集电极; （d）在由杂质形成的n +层上沉积氧化物膜后，形成双极晶体管的CMOS栅极和发射极; （e）形成PMOS，NMOS的源极和漏极; （F）CMOS的热氧化或汲取和排水，以及铝金属化。
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公开(公告)号：KR1020140063327A
公开(公告)日：2014-05-27
申请号：KR1020120130550
申请日：2012-11-16
Applicant: 한국전자통신연구원 , 단국대학교 산학협력단
IPC: H01L29/73 , H01L21/331
Abstract: A horizontal insulated gate bipolar transistor according to an embodiment of the present invention comprises: a first conductive semiconductor substrate; a second conductive drift region formed on the upper part of the first conductive semiconductor substrate; a gate electrode arranged on the first conductive semiconductor substrate; a first emitter electrode which is spaced apart from the gate electrode and is arranged on the first conductive semiconductor substrate to be adjacent to one side surface of the gate electrode; a collector electrode which is spaced apart from the gate electrode and is arranged on a second conductive semiconductor substrate to be adjacent to the other side surface of the gate electrode; a second emitter electrode arranged between the gate electrode and the collector electrode; and a trench insulation film formed between the second emitter electrode and the collector electrode in the second conductive drift region.
Abstract translation: 根据本发明实施例的水平绝缘栅双极晶体管包括：第一导电半导体衬底; 形成在第一导电半导体衬底的上部的第二导电漂移区; 布置在所述第一导电半导体衬底上的栅电极; 第一发射电极，与栅电极间隔开，并配置在第一导电半导体衬底上，与栅电极的一个侧表面相邻; 与所述栅电极间隔开并配置在与所述栅电极的另一侧面相邻的第二导电半导体衬底上的集电极; 布置在栅电极和集电极之间的第二发射极; 以及在第二导电漂移区域中形成在第二发射极和集电极之间的沟槽绝缘膜。
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公开(公告)号：KR1020070061264A
公开(公告)日：2007-06-13
申请号：KR1020060076773
申请日：2006-08-14
Applicant: 한국전자통신연구원
IPC: H01L27/04
Abstract: A triple well p-type low voltage triggered ESD protection device is provided to perform an operation at a low trigger voltage, to minimize parasitic capacitance, and to obtain a fast response speed to an ESD pulse. A deep n-type well(30) is formed on a p-type substrate(20). An n-type well(40) and a p-type well(50) are formed within the deep n-type well. A bias applying region is formed to apply directly a bias voltage to the p-type well. The bias applying region is formed with a p+ diffusion region(80) which is formed at a junction side of the n-type well and the p-type well.
Abstract translation: 提供三阱p型低电压触发ESD保护装置，以在低触发电压下执行操作，以最小化寄生电容，并获得对ESD脉冲的快速响应速度。 在p型衬底（20）上形成深n型阱（30）。 在深n型井内形成n型阱（40）和p型阱（50）。 形成偏置施加区域以直接施加偏压到p型阱。 偏置施加区域形成有形成在n型阱和p型阱的接合侧的p +扩散区（80）。
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