公开(公告)号：US07602062B1

公开(公告)日：2009-10-13

申请号：US11201515

申请日：2005-08-10

Applicant: Wen-Chou Wang

Inventor： Wen-Chou Wang

IPC: H01L21/00

CPC classification number: H01L23/49822 ,  H01L23/145 ,  H01L23/49827 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2924/12044 ,  H01L2924/15311 ,  H05K1/0271 ,  H05K1/0366 ,  H05K3/4644 ,  H05K3/4688 ,  H05K2201/0209 ,  H05K2201/068 ,  H05K2201/09327 ,  H01L2924/00012

Abstract: Multi-layered, organic build-up semiconductor package substrates have build-up layers with layers of both fibrous organic dielectric material and non-fibrous organic dielectric material. Non-fibrous dielectric material layers are positioned below the signal metal layers and fibrous dielectric material layers are positioned below the power/ground plane metal layers. The package substrate combines in a single package substrate the advantages of rigidity, strength and relatively low CTE of a fibrous material with the capacity of a non-fibrous material to achieve fine resolution signal metal lines.

Abstract translation: 多层有机聚集半导体封装衬底具有层叠有纤维有机电介质材料和非纤维有机电介质材料的堆积层。 非纤维介电材料层位于信号金属层的下方，并且纤维介电材料层位于电力/接地平面金属层下方。 封装衬底在单个封装衬底中结合了纤维材料的刚度，强度和相对低的CTE的优点，具有非纤维材料的能力以实现精细分辨率信号金属线。

公开(公告)号：US07448132B2

公开(公告)日：2008-11-11

申请号：US11537754

申请日：2006-10-02

Applicant: Joel R. Goergen

Inventor： Joel R. Goergen

IPC: H01K3/10

CPC classification number: H05K3/4688 ,  H05K1/0218 ,  H05K1/024 ,  H05K1/0243 ,  H05K1/0271 ,  H05K1/116 ,  H05K3/382 ,  H05K3/429 ,  H05K3/4626 ,  H05K3/4641 ,  H05K2201/0209 ,  H05K2201/044 ,  H05K2201/0723 ,  H05K2201/09236 ,  H05K2201/093 ,  H05K2201/09309 ,  H05K2201/09318 ,  H05K2201/09327 ,  H05K2201/09354 ,  H05K2201/09381 ,  H05K2201/09454 ,  H05K2201/09636 ,  H05K2201/09663 ,  H05K2201/09718 ,  H05K2201/09781 ,  H05K2203/061 ,  Y10T29/49117 ,  Y10T29/49128 ,  Y10T29/49155 ,  Y10T29/49156 ,  Y10T29/49162 ,  Y10T29/49163 ,  Y10T29/49165

Abstract: The disclosed board fabrication techniques and design features enable the construction of a reliable, high-layer-count, and economical backplane for routers and the like that require a large number of signaling paths across the backplane at speeds of 2.5 Gbps or greater, as well as distribution of significant amounts of power to router components. The disclosed techniques and features allow relatively thick (e.g., three- or four-ounce copper) power distribution planes to be combined with large numbers of high-speed signaling layers in a common backplane. Using traditional techniques, such a construction would not be possible because of the number of layers required and the thickness of the power distribution layers. The disclosed embodiments use novel layer arrangements, material selection, processing techniques, and panel features to produce the desired high-speed layers and low- noise high-power distribution layers in a single mechanically stable board.

Abstract translation: 所公开的板制造技术和设计特征使得能够构建用于路由器等的可靠的，高层次的和经济的背板，其需要以2.5Gbps或更高的速度跨越背板的大量信令路径，以及 作为路由器组件的大量功率分配。 所公开的技术和特征允许相对较厚（例如，三或四盎司铜）功率分配平面与公共背板中的大量高速信号层组合。 使用传统技术，由于需要的层数和配电层的厚度，这种结构将是不可能的。 所公开的实施例使用新颖的层布置，材料选择，处理技术和面板特征来在单个机械稳定的板中产生期望的高速层和低噪声大功率分配层。

公开(公告)号：US07301780B2

公开(公告)日：2007-11-27

申请号：US11414548

申请日：2006-05-01

Applicant: Shadi A. AbuGhazaleh ,  Robert C. Baxter ,  Rehan Mahmood ,  Alan C. Miller ,  Michael R. O'Connor

Inventor： Shadi A. AbuGhazaleh ,  Robert C. Baxter ,  Rehan Mahmood ,  Alan C. Miller ,  Michael R. O'Connor

IPC: H05K7/00

CPC classification number: H05K1/0228 ,  H05K1/0231 ,  H05K1/0298 ,  H05K1/162 ,  H05K2201/0723 ,  H05K2201/09327 ,  H05K2201/10189 ,  H05K2201/10689 ,  Y10S439/941

Abstract: A compensating advanced feature patch panel that can include removable modular or fixed electronic components located directly on the patch panel which are separately or in combination capable of providing advanced features such as device detection and power insertion. The patch panel provides communications between an insulation displacement connector (IDC) at a PD/User end, and any standard interface type using unshielded twisted pair cables, such as an RJ45 connector at a switch end at performance levels of at least category 3, 5, 6 e, 6 and/or higher (e.g. 6 e or 7) and equivalent performance levels by compensating for the active electronics used in providing advanced features. Compensation is achieved in part through the separation and isolation of active and communication circuit elements.

Abstract translation: 补偿高级功能接线板，其可以包括直接位于接线板上的可拆卸模块或固定电子部件，其分开地或组合地能够提供诸如设备检测和功率插入的高级特征。 接线板提供PD /用户端的绝缘位移连接器（IDC）与使用非屏蔽双绞线电缆的任何标准接口类型之间的通信，例如在开关端的RJ45连接器，性能水平至少为3,5 ，6 e，6和/或更高（例如6 e或7）和等效性能水平，通过补偿用于提供高级功能的有源电子元件。 补偿部分通过主动和通信电路元件的分离和隔离来实现。

公开(公告)号：US07301775B2

公开(公告)日：2007-11-27

申请号：US11515763

申请日：2006-09-06

Applicant: Hiroshi Isoda

Inventor： Hiroshi Isoda

IPC: H05K7/02 ,  H03K9/00

CPC classification number: H04B1/28 ,  H01L23/50 ,  H01L23/552 ,  H01L23/66 ,  H01L2223/6616 ,  H01L2223/6677 ,  H01L2224/16 ,  H01L2924/01079 ,  H01L2924/15153 ,  H01L2924/1517 ,  H01L2924/15311 ,  H01L2924/19041 ,  H01L2924/19105 ,  H01L2924/30107 ,  H01L2924/3011 ,  H01L2924/3025 ,  H05K1/0218 ,  H05K1/0237 ,  H05K1/0298 ,  H05K2201/0723 ,  H05K2201/09327

Abstract: A tuner section is provided on one surface of a multilayered substrate, and a demodulating section on another surface of the multilayered substrate. The multilayered substrate further includes: an analog GND layer connected to the tuner section; a digital GND layer connected to the demodulating section; a shield GND layer which is provided between the analog GND layer and the digital GND layer; and insulation layers each provided (i) between the analog GND layer and shield GND layer, or (ii) between the digital GND layer and shield GND layer so as to electrically disconnect the shield GND layer from the analog GND layer and the digital GND layer. This allows the tuner section and the demodulating section to be respectively arranged on different surfaces of the substrate, for the purpose of downsizing of the receiving device, and yet allows the tuner section from being influenced by a harmonic signal generated in the demodulating section.

公开(公告)号：US20070244684A1

公开(公告)日：2007-10-18

申请号：US11405242

申请日：2006-04-17

Applicant: Rajen Murugan ,  Jimmy Pike ,  Abeye Teshome

Inventor： Rajen Murugan ,  Jimmy Pike ,  Abeye Teshome

IPC: G06F17/50

CPC classification number: G06F17/5036 ,  H05K1/0216 ,  H05K1/0237 ,  H05K3/0005 ,  H05K3/429 ,  H05K2201/09327

Abstract: A methodology may be used that takes into account the inductive coupling of current transients on the power rails of a printed circuit board (PCB) that may be coupled to the barrel of a via. By taking into account the coupling of the current transients on the power rails of the PCB, more accurate and realistic modeling results may be obtained. Inductive coupling of the current transients from the power rails may be more pronounced at higher frequencies and may be additive for more layer transitions (e.g., more via transitions) of the PCB.

Abstract translation: 可以使用考虑到可以耦合到通孔的筒的印刷电路板（PCB）的电源轨上的电流瞬变的电感耦合的方法。 通过考虑PCB上电源线上的电流瞬变的耦合，可以获得更精确和逼真的建模结果。 来自电源轨的电流瞬变的感性耦合可能在较高频率下更为显着，并且可能对于PCB的更多层转变（例如更多的经由转变）而言是相加的。

公开(公告)号：US20070109726A1

公开(公告)日：2007-05-17

申请号：US11281688

申请日：2005-11-17

Applicant: Wiren Becker ,  Bruce Chamberlin ,  Roland Frech ,  Andreas Huber ,  George Katopis ,  Erich Klink ,  Andreas Rebmann ,  Thomas-Michael Winkel

Inventor： Wiren Becker ,  Bruce Chamberlin ,  Roland Frech ,  Andreas Huber ,  George Katopis ,  Erich Klink ,  Andreas Rebmann ,  Thomas-Michael Winkel

IPC: H02B1/00

CPC classification number: H05K1/0262 ,  H05K1/0298 ,  H05K1/141 ,  H05K2201/093 ,  H05K2201/09327 ,  H05K2201/09663

Abstract: The present invention relates to computer hardware design and in particular to a printed circuit board comprising wiring dedicated to supply electric board components such as integrated circuits with at least three different reference planes. In order to provide a printed circuit board having an improved signal return path for basically all relevant signal layers at transitions between card, connector, module and chip while still holding the cross-section structure simple, it is proposed to establish a layer structure wherein a) a split voltage plane is located adjacent to one side of one of said reference planes and comprises conducting portions for all of said at least three different voltage levels in respective plane parts, and b) a signal layer being located adjacent to said reference planes.

Abstract translation: 本发明涉及计算机硬件设计，特别是涉及一种印刷电路板，其中印刷电路板包括专用于提供诸如具有至少三个不同参考平面的集成电路的电路板部件的布线。 为了提供一种印刷电路板，其具有改进的信号返回路径，用于基本上在卡，连接器，模块和芯片之间的转变处的所有相关信号层，同时仍然保持横截面结构简单，因此建议建立层结构，其中 ）分裂电压平面位于所述参考平面中的一个的一侧附近，并且包括用于各个平面部分中的所有所述至少三个不同电压电平的导电部分，以及b）位于所述参考平面附近的信号层。

公开(公告)号：US20060256540A1

公开(公告)日：2006-11-16

申请号：US11414548

申请日：2006-05-01

Applicant: Shadi AbuGhazaleh ,  Robert Baxter ,  Rehan Mahmood ,  Alan Miller ,  Michael O'Connor

Inventor： Shadi AbuGhazaleh ,  Robert Baxter ,  Rehan Mahmood ,  Alan Miller ,  Michael O'Connor

IPC: H05K7/06 ,  H05K7/10

CPC classification number: H05K1/0228 ,  H05K1/0231 ,  H05K1/0298 ,  H05K1/162 ,  H05K2201/0723 ,  H05K2201/09327 ,  H05K2201/10189 ,  H05K2201/10689 ,  Y10S439/941

Abstract: A compensating advanced feature patch panel that can include removable modular or fixed electronic components located directly on the patch panel which are separately or in combination capable of providing advanced features such as device detection and power insertion. The patch panel provides communications between an insulation displacement connector (IDC) at a PD/User end, and any standard interface type using unshielded twisted pair cables, such as an RJ45 connector at a switch end at performance levels of at least category 3, 5, 6e, 6 and/or higher (e.g. 6e or 7) and equivalent performance levels by compensating for the active electronics used in providing advanced features. Compensation is achieved in part through the separation and isolation of active and communication circuit elements.

Abstract translation: 补偿高级功能接线板，其可以包括直接位于接线板上的可拆卸模块或固定电子部件，其分开地或组合地能够提供诸如设备检测和功率插入的高级特征。 接线板提供PD /用户端的绝缘位移连接器（IDC）与使用非屏蔽双绞线电缆的任何标准接口类型之间的通信，例如在开关端的RJ45连接器，性能水平至少为3,5 ，6e，6和/或更高（例如6e或7）和等效的性能水平，通过补偿用于提供高级功能的有源电子元件。 补偿部分通过主动和通信电路元件的分离和隔离来实现。

公开(公告)号：US20060076668A1

公开(公告)日：2006-04-13

申请号：US11244333

申请日：2005-10-06

Applicant: Sung-ki Kim

Inventor： Sung-ki Kim

IPC: H01L23/52 ,  H05K7/06

CPC classification number: H05K1/0216 ,  H05K1/0298 ,  H05K2201/0191 ,  H05K2201/09327

Abstract: A multi-layer PCB includes a first signal layer, a ground layer, a second signal layer, a third signal layer, an electric power layer, and a fourth signal layer, including a first insulating layer arranged between the first signal layer and the ground layer; a second insulating layer arranged between the ground layer and the second signal layer; a third insulating layer arranged between the second signal layer and the third signal layer; a fourth insulating layer arranged between the third signal layer and the electric power layer; and a fifth insulating layer arranged between the electric power layer and the fourth signal layer, wherein at least one of the first signal layer, the second signal layer, the third signal layer, and the fourth signal layer includes a pattern.

Abstract translation: 多层PCB包括第一信号层，接地层，第二信号层，第三信号层，电力层和第四信号层，包括布置在第一信号层和地之间的第一绝缘层 层; 布置在所述接地层和所述第二信号层之间的第二绝缘层; 布置在所述第二信号层和所述第三信号层之间的第三绝缘层; 布置在所述第三信号层和所述电力层之间的第四绝缘层; 以及布置在所述电力层和所述第四信号层之间的第五绝缘层，其中所述第一信号层，所述第二信号层，所述第三信号层和所述第四信号层中的至少一个包括图案。

公开(公告)号：US20060003612A1

公开(公告)日：2006-01-05

申请号：US10884330

申请日：2004-07-02

Applicant: David Spengler

Inventor： David Spengler

IPC: H01R13/648

CPC classification number: G06F1/189 ,  G06F1/187 ,  H01R13/6471 ,  H05K1/0216 ,  H05K2201/09327

Abstract: An electronics cabinet is provided comprising an electrical connector in electrical communication with a printed circuit board (PCB) comprising a PCB power plane, the connector comprising a plurality of power contacts defining a connector power plane adapted for receiving a substantially even power load distribution from the PCB power plane among the power contacts.

公开(公告)号：US20050225955A1

公开(公告)日：2005-10-13

申请号：US10821458

申请日：2004-04-09

Applicant: John Grebenkemper ,  Frank Mikalauskas ,  Srinivasan Venkataraman ,  Jonathan Buck

Inventor： John Grebenkemper ,  Frank Mikalauskas ,  Srinivasan Venkataraman ,  Jonathan Buck

IPC: G01S13/00 ,  H05K1/00 ,  H05K1/02 ,  H05K7/02 ,  H05K7/06 ,  H05K7/08 ,  H05K7/10

CPC classification number: H05K1/0218 ,  H05K1/0298 ,  H05K2201/0723 ,  H05K2201/09309 ,  H05K2201/09327

Abstract: A printed circuit board includes a power plane and a ground reference plane that includes two opposite sides. The power plane is positioned proximate one side of the ground reference plane. A signal layer is positioned proximate the other side of the ground reference plane to isolate the power plane from the signal layer. Any noise on the power plane or the signal layer is thus isolated by the intervening ground plane.

Abstract translation: 印刷电路板包括电源平面和包括两个相对侧的接地参考平面。 电源平面位于接地参考平面的一侧。 信号层位于接地参考平面的另一侧附近，以将功率平面与信号层隔离。 电力平面或信号层上的任何噪声因此被插入的接地层隔离。