公开(公告)号：JPH02288931A

公开(公告)日：1990-11-28

申请号：JP27360289

申请日：1989-10-20

Applicant: TANDEM COMPUTERS INC

Inventor： ROBAATO DABURIYUU HOOSUTO

IPC: G06F12/08 ,  G06F12/0862 ,  G06F12/0886 ,  G06F12/0895 ,  G06F12/109

Abstract: PURPOSE: To take out words of a prescribed sequence in one memory cycle by taking the word addressed by a received memory word address as a first read data value. CONSTITUTION: Words of a prescribed multi-word data unit(MWDU) 14 are stored in another memory unit, and this unit has each storage locations 12 addressed by a multi-word field(MWF) of word addresses of words in the prescribed MWDU 14. Hardware for address processing uses the word address of the first word of a prescribed sequence to generate one set or changed MWF provided in the address port of the memory unit. A data supply device connects the output of the memory unit to an output bus and transfers sequential words to this bus in the correct order. Thus, words of the prescribed sequence are taken out in one memory cycle.

公开(公告)号：JPH02202638A

公开(公告)日：1990-08-10

申请号：JP32246389

申请日：1989-12-11

Applicant: TANDEM COMPUTERS INC

Inventor： RICHIYAADO DABURIYUU KATSUTSU ,  DAGURASU II JIYUUETSUTO ,  RICHIYAADO EE SAUSUWAASU ,  KENISU SHII DEIBETSUKAA ,  NIKIIRU EE MEETA ,  JIYON DEIBITSUDO ARISON ,  ROBAATO DABURIYUU HOOSUTO

IPC: G06F9/52 ,  G06F11/00 ,  G06F11/10 ,  G06F11/14 ,  G06F11/16 ,  G06F11/18 ,  G06F11/20 ,  G06F15/17 ,  G11C29/00

Abstract: PURPOSE: To prevent the synchronizing operation from being extremely drifted away by providing an interrupt circuit which responds to the count selected in each of all counters. CONSTITUTION: A cycle counter 71 is so set that it overflows at one point before expiration of a maximum interrupt latency period. An interrupt synchronizing request signal and an interrupt signal are generated by the overflow to force resynchronization. When a processor 40 supplies an interrupt, a code in an interrupt routine forces the occurrence of an event. The synchronizing request signal internally generated in this manner causes resynchronization with the event generated by the interrupt routine.

公开(公告)号：JPH02168722A

公开(公告)日：1990-06-28

申请号：JP28870188

申请日：1988-11-15

Applicant: TANDEM COMPUTERS INC

Inventor： OORANGUZEBU KEI KAAN

IPC: H03K19/003 ,  H03K19/018

Abstract: PURPOSE: To attain accurately controlled voltage conversion even under wide variation in respective variables such as manufacturing, processes, temperature, and voltage by automatically shifting ECL voltage reference also at a suitable rate when the level of TTL reference is slightly shifted so as to compensate the initial shift of the TTL reference. CONSTITUTION: A clamp type level shift comparator is formed by a resistor R1 and transistors(TRs) Q1 to Q3. When a comparatively large input voltage change is generated in the circuit, sufficiently controlled small voltage oscillation is generated on a node 1. A self-centering type reference threshold converter is formed by TRs Q7, Q8, Q10, Q15 and resistors R5, R6, R12, and when TTL reference voltage is changed due to a temperature change or other factors, ECL voltage also is changed only by a fixed ratio of the change in the TTL reference voltage. The devices R1, Q1 to Q3 are used for the generation of comparatively small and sufficietly controlled ECL voltage from the shift of the large TTL input voltage on an emitter-connected node expressed as the node 1.

公开(公告)号：JPH02112340A

公开(公告)日：1990-04-25

申请号：JP14395889

申请日：1989-06-06

Applicant: TANDEM COMPUTERS INC

Inventor： ROBAATO JIEI SUTETEIINA

IPC: H03K17/00 ,  H04B3/00 ,  H04J99/00

Abstract: PURPOSE: To maximize the number of links to be formed by connecting a right side matrix connection system and a left side matrix connection system which have one set consisting of N taps respectively to both side terminals of unique pairs of wires. CONSTITUTION: Each of matrix connection systems 10, 10' has N taps 18 and n contacts 16, respective contacts 16 are connected to different wires in a conductive line and respective taps 18 are connected to unique pairs of contacts 16. The right side matrix connection system 10' is connected to right side terminals 16 consisting of n wires 14 and the left side matrix connection system 10 is connected to the left side terminals of wires 14. Unique and independent two- wire type wires are formed correspondingly to the right and left taps connected to the same unique wire pair. Consequently N independent two-wire links can be formed between two communication junctions connected by an n-wire conductive link and the conductive line can efficiently be utilized.

公开(公告)号：JPH01280842A

公开(公告)日：1989-11-13

申请号：JP30046588

申请日：1988-11-28

Applicant: TANDEM COMPUTERS INC

Inventor： MAATEIN DABURIYUU SANAA

IPC: G06F11/22 ,  G01R31/3185

Abstract: PURPOSE: To eliminate data loss due to clocking delay by making a sub chain for receiving the different type with less delay of scanning clocks appear after a scanning line. CONSTITUTION: The distribution of the sub chains 12, 14, 16, 18 and 20 in the entire scanning line 10 formed when SCAN EN is asserted is decided by the different type of system clocks(SYSCLK) received by the sub chains 12, 14, 16, 18 and 20. The sub chains 12, 14, 16, 18 and 20 receive the scanning line of the different type with the least delay. Thus, the sub chain 20 for receiving the SYSCLK of the different type without the delay is placed at the end of the scanning line. Thus, the data loss due to delay clocks is eliminated.

公开(公告)号：JPH01258057A

公开(公告)日：1989-10-16

申请号：JP28230688

申请日：1988-11-08

Applicant: TANDEM COMPUTERS INC

Inventor： ROBAATO DABURIYUU HOOSUTO

IPC: G06F11/18 ,  G06F9/52 ,  G06F11/16 ,  G06F15/17 ,  G11C29/00

Abstract: PURPOSE: To guarantee the maintainability of data by counting events such as writing operations instructed for every processor and interrupting a processing when the number of event to be counted of a pertinent processor is larger than the number of event to be counted of an other processor. CONSTITUTION: Synchronizing requests are received by CPU 6, 8 and 10 and each of the CPUs executes parts of different codes. The CPU 6 becomes a wating state because an event 4 is detected. The CPU 8 and the CPU 10 become waiting states by the detection of an event 5 and the detection of an event 6, respectively. Because the number of event to be counted of the CPU 6 is smaller than that of the CPU 10, the CPU 6 restarts the execution of an instruction and becomes the waiting state by the detection of an event 5. When the CPU 6 is still delayed than the CPU 10, an execution instruction is restarted, the event 5 is detected and the CPU 6 becomes the waiting state again. Also the CPU 8 takes the same processing sequence. Thus, when the count of each event becomes equal, each processor restarts an execution by the synchronizing external interruption signal at a point of common time.

公开(公告)号：JPH0139132B2

公开(公告)日：1989-08-18

申请号：JP20389784

申请日：1984-09-28

Applicant: TANDEM COMPUTERS INC

Inventor： ROBAATOITSUTEINGU HOOSUTO ,  RICHAADO RII HAARISU

IPC: G06F20060101 ,  G06F9/00 ,  G06F9/22 ,  G06F9/26 ,  G06F9/38 ,  G06F9/40 ,  G06F9/42

公开(公告)号：JPH01188953A

公开(公告)日：1989-07-28

申请号：JP30046088

申请日：1988-11-28

Applicant: TANDEM COMPUTERS INC

Inventor： UIN EMU CHIYAN

IPC: G06F11/10 ,  G06F11/16 ,  G11B20/18

Abstract: PURPOSE: To provide a data maintaining device having an excellent fault allowable range capability by providing two control means for error correction code generation and error detection and generating an error correction code by one of these means and detecting an error by the other. CONSTITUTION: When data transmitted from a CPU through a bus 10 is stored in a storage device 14, one of two device control units 40a and 40b generates the code and adds it to this data. At this time, the other device control unit uses the added correction code to detect an error, thereby inspecting the function of the device control unit for code generation. One device control unit may generate the error correction code and detect an error even if the other is faulty.

公开(公告)号：JPH01162012A

公开(公告)日：1989-06-26

申请号：JP28869988

申请日：1988-11-15

Applicant: TANDEM COMPUTERS INC

Inventor： OORANGUZEBU KEI KAAN

IPC: H03K19/013 ,  H03K19/0175 ,  H03K19/018 ,  H03K19/082

Abstract: PURPOSE: To increase a speed of transition from 'tri-state' mode into 'operating mode' considerably and to improve delay performance of the transition from 'tri-state' mode into 'operating mode' by forming a circuit to drive a TTL bus from an ECL circuit so as to eliminate the need for a converter and a buffer. CONSTITUTION: A true ECL/true TTL converter 11 is made up of three transistors(TRs) Q1-Q3 forming an inverter. Then a base voltage of the TRQI is changed by ±0.5Vbe around an ECL standard voltage Vr1. Thus, in the case of Vb(Q1)>Vr1, the TRQ1 produces a full Vbe and reaches a forward conduction state, then a relation of TR (Q2)

公开(公告)号：JPS6446834A

公开(公告)日：1989-02-21

申请号：JP7169388

申请日：1988-03-25

Applicant: TANDEM COMPUTERS INC

Inventor： DANIERU II RENOSUKII

IPC: G06F9/32

Abstract: PURPOSE: To eliminate the necessity of additional hardware and timing delay by using a specified group relative address specification system. CONSTITUTION: A memory 10 has a branch instruction(BR) 12, a literal field(LIT) 14 and an address specification instruction TARG 16. The upper bits of a 1st address are converted into the upper bits of a 2nd address by hardware controlled by a selected numeral within the LIT 14 including numerals supplied from the external. The converted upper bits of the 1st address and a subset of numerals supplied by the LIT 14 are combined to form the 2nd selected address. Consequently, the offset of both of positive and negative values from an optional program counter address(PC) value can be guaranteed without requiring excess hardware and time delay.