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公开(公告)号：KR1019990035568A
公开(公告)日：1999-05-15
申请号：KR1019970057390
申请日：1997-10-31
Applicant: 삼성전자주식회사
Inventor： 김남석
IPC: H01L23/40
Abstract: 본 발명에 의한 패키지는 외부에 노출된 히트싱크의 하부면에 딤플(dimple)을 형성하여 표면적을 확대시키고 리드프레임의 내부리드와 히트싱크(heat sink)를 열전도성 접착테이프에 접착하며, PECVD(plasma enhanced chemical vapor deposition)에 의해 히트싱크의 하부면에 다이아몬드 박막을 형성한다.
따라서, 본 발명은 패키지의 사이즈를 확대하지 않고도 방열효과를 증가시켜 제품의 신뢰성을 향상시킨다.-
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公开(公告)号：KR1020110123526A
公开(公告)日：2011-11-15
申请号：KR1020100043052
申请日：2010-05-07
Applicant: 삼성전자주식회사
CPC classification number: H01L24/02 , H01L23/3192 , H01L24/05 , H01L24/13 , H01L2224/0236 , H01L2224/024 , H01L2224/0401 , H01L2224/05012 , H01L2224/05548 , H01L2224/13021 , H01L2224/13022 , H01L2924/01005 , H01L2924/01006 , H01L2924/01033 , H01L2924/01047 , H01L2924/01082 , H01L2924/01322 , H01L2924/014 , H01L2924/14 , H01L2924/181 , H01L21/50 , H01L21/52 , H01L21/56 , H01L2924/00
Abstract: PURPOSE: A wafer level package and a formation method thereof are provided to arrange a second encapsulated pattern with moisture permeability while filling a gap, thereby preventing deviation of an external connection terminal. CONSTITUTION: A rewiring pattern(60) is arranged on a semiconductor device. A first encapsulated pattern(70) is formed in order to be directly touched with the rewiring pattern. The first encapsulated pattern comprises a via hole. The external connection terminal(80) is arranged on the rewiring pattern within the via hole. The external connection terminal includes a gap in order to be separated from the upper end part of a lateral wall of the via hole.
Abstract translation: 目的：提供晶片级封装及其形成方法，以在填充间隙时布置具有透湿性的第二封装图案，从而防止外部连接端子的偏差。 构成：在半导体器件上布置重新布线图案（60）。 形成第一封装图案（70）以便用重新布线图案直接接触。 第一封装图案包括通孔。 外部连接端子（80）布置在通孔内的重新布线图案上。 外部连接端子包括用于与通孔的侧壁的上端部分离的间隙。
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公开(公告)号：KR1020110051588A
公开(公告)日：2011-05-18
申请号：KR1020090108237
申请日：2009-11-10
IPC: C25D3/38
CPC classification number: C25D17/005 , C25D17/001 , C25D17/008 , C25D17/02 , C25D21/10
Abstract: PURPOSE: A device and a method for plating substrates are provided to perform plating processes without the turning of substrates since the plated surface of a substrate is faced upward and supported. CONSTITUTION: A substrates plating device comprises a substrate support member, an anode electrode, a power source, a plating liquid feed member, a plating bath(240), and a first drive unit. The substrate support member supports the substrate so the plated surface of the substrate is faced upward. The anode electrode is placed on the top of the substrate support member. The power source applies voltage on anode electrode and substrate. The plating liquid supply member supplies the plating liquid to the substrate. The plating liquid feed member is placed on the top of the anode electrode. The plating liquid feed member comprises a plating liquid nozzle. The plating liquid nozzle discharges plating liquid downward. The plating bath has an opened lower part. The plating bath accepts the plating liquid nozzle and an anode electrode inside. The first drive unit elevates the substrate support member to open and close the opened lower part of the plating bath.
Abstract translation: 目的：提供一种用于电镀基板的装置和方法，用于执行电镀工艺而不转动基板，因为基板的镀覆表面面向上并被支撑。 构成：基板电镀装置包括基板支撑构件，阳极电极，电源，电镀液供给构件，电镀槽（240）和第一驱动单元。 衬底支撑构件支撑衬底，使得衬底的电镀表面面向上。 阳极被放置在基板支撑件的顶部上。 电源在阳极电极和基板上施加电压。 电镀液供给部件将电镀液供给到基板。 电镀液供给部件配置在阳极电极的顶部。 电镀液供给部件包括电镀液喷嘴。 电镀液喷嘴向下排放电镀液。 电镀浴具有打开的下部。 镀浴在内部接受电镀液喷嘴和阳极电极。 第一驱动单元升高基板支撑构件以打开和关闭电镀槽的打开的下部。
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公开(公告)号：KR1020090056044A
公开(公告)日：2009-06-03
申请号：KR1020070123003
申请日：2007-11-29
Applicant: 삼성전자주식회사
CPC classification number: H01L23/3128 , H01L23/055 , H01L23/10 , H01L24/81 , H01L25/0657 , H01L25/50 , H01L2224/97 , H01L2225/06572 , H01L2924/01006 , H01L2924/01013 , H01L2924/01029 , H01L2924/01033 , H01L2924/09701 , H01L2924/14 , H01L2224/81 , H01L2924/00
Abstract: A semiconductor device package and a method of fabricating the same are provided to prevent bend of a capping layer and a substrate by selecting a material of the capping layer to minimize thermal expansion coefficient of the capping layer and each material. A via hole(103) passing through inside a substrate(100) and penetration electrode(130) is received into the via hole. A first semiconductor chip(160) is provided on the substrate and is electrically connected to the penetration electrode, and in a capping layer, a groove larger than the size of the first semiconductor chip. The capping layer is formed on the substrate so that the first semiconductor chip is received to the groove, and a second semiconductor chip is separated from the first semiconductor chip while the substrate is installed between them, and it is electrically connected with the first semiconductor chip through at least one of the penetration electrodes.
Abstract translation: 提供一种半导体器件封装及其制造方法，以通过选择覆盖层的材料来防止封盖层和基板的弯曲，以使封盖层和每种材料的热膨胀系数最小化。 穿过基板（100）和穿透电极（130）内部的通孔（103）被接收到通孔中。 第一半导体芯片（160）设置在基板上并与穿透电极电连接，并且在封盖层中，具有大于第一半导体芯片的尺寸的凹槽。 覆盖层形成在基板上，使得第一半导体芯片被接收到沟槽中，并且第二半导体芯片与第一半导体芯片分离，同时将基板安装在它们之间，并且其与第一半导体芯片 穿过至少一个穿透电极。
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Patent Agency Ranking
公开(公告)号：KR1020090047776A
公开(公告)日：2009-05-13
申请号：KR1020070113799
申请日：2007-11-08
Applicant: 삼성전자주식회사
CPC classification number: H01L21/76898 , H01L23/481 , H01L25/0657 , H01L25/50 , H01L2224/16 , H01L2225/06513 , H01L2225/06517 , H01L2225/06541 , H01L2924/15311
Abstract: 반도체 소자 및 그 형성 방법을 제공한다. 이 소자는 반도체 기판을 관통하는 제1 비아홀과, 소자 절연층 및 패드를 연속적으로 관통하는 제2 비아홀내에 배치된 관통 전극을 포함한다. 관통 전극은 패드로부터 돌출된 돌출부를 포함하며, 적어도 관통 전극의 돌출부의 표면은 내산화성 도전 물질로 형성된다.
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公开(公告)号：KR1020080105242A
公开(公告)日：2008-12-04
申请号：KR1020070052543
申请日：2007-05-30
Applicant: 삼성전자주식회사
CPC classification number: H01L2224/16 , H01L2224/48095 , H01L2224/4847 , H01L2924/01079 , H01L2924/10253 , H01L2924/15311 , H01L2924/181 , H01L2924/00014 , H01L2924/00 , H01L2924/00012
Abstract: A chip scale semiconductor package is provided to reduce the height of semiconductor package as same as the planarization layer by reducing the planarization layer arranged between the substrate and the rerouting line of the semiconductor chip. A semiconductor package(900) comprises the substrate(100), the re-ordering wiring(300), the solder ball(400), the insulating layer(500). A semiconductor chip(200) including the integrated circuit and the connection pad(220) for exchanging the electric signal the integrated circuit is fixed. The re-ordering wiring is consecutively arranged along the top of substrate and top of the semiconductor chip. The re-ordering wiring has the wiring step height between the first area positioned on the top of the semiconductor chip and the second part positioned on the top of substrate. The re-ordering wiring is electrically connected with the connection pad. The solder ball comprises the connection part(410), and the connector area(420). The connection part is electrically connected to the re-ordering wiring. The connector area is connected to the connection part and the connector area electrically connects the external signal source and the semiconductor chip. The insulating layer is arranged on the substrate. The insulating layer electrically insulates the semiconductor chip and the re-ordering wiring.
Abstract translation: 提供了一种芯片级半导体封装，通过减少布置在半导体芯片的基板和重新布线之间的平坦化层，来降低与平坦化层相同的半导体封装的高度。 半导体封装（900）包括基板（100），重新排序布线（300），焊球（400），绝缘层（500）。 包括集成电路的半导体芯片（200）和用于将集成电路交换电信号的连接焊盘（220）固定。 重新排序的布线沿着衬底的顶部和半导体芯片的顶部连续布置。 再排序布线具有位于半导体芯片顶部的第一区域和位于基板顶部的第二部分之间的布线步长。 重新排序的接线与连接垫电连接。 焊球包括连接部分（410）和连接器区域（420）。 连接部分电连接到重新订购的布线。 连接器区域连接到连接部分，并且连接器区域电连接外部信号源和半导体芯片。 绝缘层设置在基板上。 绝缘层将半导体芯片和重新排序的布线电绝缘。
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公开(公告)号：KR1020080102815A
公开(公告)日：2008-11-26
申请号：KR1020070049766
申请日：2007-05-22
Applicant: 삼성전자주식회사
CPC classification number: H01L23/3128 , H01L23/5389 , H01L24/24 , H01L25/105 , H01L2224/24226 , H01L2224/32225 , H01L2224/73267 , H01L2224/82039 , H01L2224/82047 , H01L2224/92244 , H01L2225/1035 , H01L2225/1058 , H01L2924/01005 , H01L2924/01006 , H01L2924/01033 , H01L2924/01038 , H01L2924/01047 , H01L2924/01074 , H01L2924/01078 , H01L2924/14 , H01L2924/15311 , H01L2924/15331 , H01L2924/3011 , H01L2924/351 , H01L2924/00
Abstract: A semiconductor package and a manufacturing method thereof are provided to improve the combination confidence by the external force by forming the upper film and the lower film with the material having low modulus. A manufacturing method of the semiconductor package includes the step for forming package units including the semiconductor chip(20) interposed between the underlayer(10) and the upper film(30); the step for laminating successively the package units onto the top of the substrate. The upper film and the lower film are formed of the material having modulus lower than the semiconductor chip.
Abstract translation: 提供一种半导体封装及其制造方法，通过用具有低模量的材料形成上膜和下膜来改善外力的组合置信度。 半导体封装的制造方法包括形成封装单元的步骤，该封装单元包括置于底层（10）和上膜（30）之间的半导体芯片（20）; 将封装单元依次层压到基板的顶部上的步骤。 上膜和下膜由模量低于半导体芯片的材料形成。
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公开(公告)号：KR1020080084231A
公开(公告)日：2008-09-19
申请号：KR1020070025632
申请日：2007-03-15
Applicant: 삼성전자주식회사
IPC: H01L23/12
CPC classification number: H01L2224/16145 , H01L25/074 , H01L23/5222 , H01L23/5329 , H01L24/10
Abstract: A stacked semiconductor device is provided to effectively increase integration of a semiconductor device and a semiconductor package by forming a semiconductor device in one process wherein a plurality of unit device layers are stacked in the semiconductor device. A lower device(D1) is positioned on the lower surface of an intermediate insulation layer(300). A lower pad(210) is electrically connected to the lower device. An upper device(D2) is positioned on the upper surface of the interlayer dielectric. An upper pad(410) is electrically connected to the upper device. The lower pad can be electrically connected to the upper pad. The lower and upper devices can have a mutually reversed layer structure.
Abstract translation: 提供一种叠层半导体器件，用于通过在半导体器件中堆叠多个单元器件层的一个工艺中形成半导体器件来有效地增加半导体器件和半导体封装的集成。 下部装置（D1）位于中间绝缘层（300）的下表面上。 下焊盘（210）电连接到下部装置。 上部装置（D2）位于层间电介质的上表面上。 上部焊盘（410）电连接到上部装置。 下垫可以电连接到上垫。 下部和上部装置可以具有相互反转的层结构。
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公开(公告)号：KR100597633B1
公开(公告)日：2006-07-05
申请号：KR1020040000517
申请日：2004-01-06
Applicant: 삼성전자주식회사
IPC: H03H3/00
CPC classification number: H04L25/0278 , H03K19/00384 , H04L25/028
Abstract: 본 발명은 임피던스 컨트롤 장치 및 그에 따른 컨트롤 방법에 관한 것으로, 본 발명에 따른 임피던스 컨트롤 장치는, 임피던스 전류를 발생시키는 전류미러부와, 트랜지스터 어레이로 구성되어 상기 임피던스 전류에 상응하는 임피던스를 갖도록 코드 발생기에 의해 컨트롤되는 적어도 하나 이상의 디텍터와, 상기 디텍터의 출력과 기준 전압을 비교하여 상기 디텍터를 구성하는 트랜지스터 어레이의 게이트 전압을 조절하기 위한 제1코드를 발생시켜 상기 디텍터의 출력을 조절하고, 상기 임피던스 전류에 근접하거나 일치되는 때에 발생된 제1코드에 응답하는 상기 디텍터의 출력과 기준전압을 비교하여, 상기 디텍터를 구성하는 트랜지스터 어레이의 사이즈를 조절하기 위한 제2코드를 발생시켜 상기 디텍터를 컨트롤하는 적어도 하나 이상의 코드 발생기를 구비함을 특징으로 한다. 본 발명에 따르면, 외부 저항이 다른 경우에도 일정한 임피던스 해상도를 가질 수 있으며, 공정 변화나 환경변화에 관계없이 일정한 임피던스 해상도를 얻을 수 있다.
임피던스, 디더링, 해상도, 게이트 전압, 트랜지스터 어레이
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