公开(公告)号：DE69811155T2

公开(公告)日：2003-10-23

申请号：DE69811155

申请日：1998-05-12

Applicant: SIEMENS AG ,  IBM

Inventor： KIRIHATA TOSHIAKI ,  DANIEL GABRIEL ,  DORTU JEAN-MARC ,  PFEFFERL KARL-PETER

IPC: G06F12/16 ,  G11C29/00 ,  G11C29/04 ,  G06F11/20

Abstract: The method of making a fault-tolerant memory device employs a variable domain redundancy replacement (VDRR) arrangement. The method includes the steps of: subdividing the memory into a plurality of primary memory arrays; defining a plurality of domains, at least one of the domains having at least a portion common to another domain to form an overlapped domain area. and wherein at least one of the domains overlaps portions of at least two of the primary arrays; allocating redundancy means to each of the domains to replace faults contained within each of the domains; and replacing at least one of the faults within one of the domains with the redundancy means coupled to the one domain, and at least one other fault of the one domain is replaced by the redundancy means coupled to another of the domains, if the at least one other fault is positioned within the overlapped domain area. Each redundancy unit supporting the primary memory arrays includes a plurality of redundant elements. Unlike the conventional fixed domain redundancy replacement scheme, redundancy units are assigned to at least two variable domains, wherein at least a portion of the domain is common to that of another domain. VDRR makes it possible to choose the most effective domain, and in particular, a smaller domain for repairing a random fault or a larger domain for repairing a clustered faults.

公开(公告)号：SG97920A1

公开(公告)日：2003-08-20

申请号：SG200004493

申请日：2000-08-14

Applicant: IBM

Inventor： COTEUS PAUL WILLIAM ,  JI BRIAN LI ,  KIRIHATA TOSHIAKI ,  ROSS JOHN MICHAEL ,  SHEN WILLIAM WU ,  HOVIS PAUL WILLIAM

IPC: G06F12/16 ,  G06F12/02 ,  G11C8/08 ,  G11C11/407

公开(公告)号：DE69625038D1

公开(公告)日：2003-01-09

申请号：DE69625038

申请日：1996-09-06

Applicant: TOSHIBA KAWASAKI KK ,  IBM

Inventor： KATOH DAISUKE ,  KIRIHATA TOSHIAKI ,  YOSHIBA MUNEHIRO

IPC: G11C11/409 ,  G11C7/10 ,  G11C11/4091 ,  G11C11/4094

Abstract: The DRAM comprises an array of memory cells in rows and columns. A word line is provided in each row and a bit line is provided in each column. Each bit line pair is coupled through a pair of high-resistance pass gates to a sense amp. During sense, the high-resistance pass gates act in conjunction with the charge stored on the bit line pair as, effectively, a high-resistance passive load for the sense amp. A control circuit selectively switches on and off bit line equalization coincident with selectively passing either the equalization voltage or set voltages to the sense amp and an active sense amp load. Further, after it is set, the sense amp is selectively connected to LDLs through low-resistance column select pass gates. Therefore, the sense amp quickly discharges one of the connected LDL pair while the bit line voltage remains essentially unchanged. Thus, data is passed from the sense amp to a second sense amplifier and off chip. After data is passed to the LDLs, the control circuit enables the active sense amp load to pull the sense amp high side to a full up level.

公开(公告)号：DE69624312D1

公开(公告)日：2002-11-21

申请号：DE69624312

申请日：1996-08-12

Applicant: IBM

Inventor： DEBROSSE JOHN KENNETH ,  KIRIHATA TOSHIAKI ,  WONG HING

IPC: G11C11/401 ,  G11C11/409 ,  G11C11/4091 ,  G11C29/50 ,  G11C29/00

Abstract: A bit line pair is coupled through a pair of high-resistance pass gates (164L,164R) to a sense amp (166). During sense, the high-resistance pass gates (164L,164R) act in conjunction with the charge stored on the bit line pair as, effectively, a high-resistance passive load for the sense amp (166). A control circuit (185) selectively switches on and off bit line equalisation coincident with selectively passing either the equalisation voltage or set voltages to the sense amp (166) and an active sense amp load (172,174). Further, after it is set, the sense amp (166) is selectively connected to LDLs (182,184) through low-resistance column select pass gates (178,180). Therefore, the sense amp (166) quickly discharges one of the connected LDL pair while the bit line voltage remains essentially unchanged. Thus, data is passed from the sense amp (166) to a second sense amplifier and off chip. After data is passed to the LDLs (182,184), the control circuit (185) enables the active sense amp load (172,174) to pull the sense amp high side to a full up level. Additionally, because the control circuit (185) uses the equalisation voltage to disable the sense amp (166), cell signal margin may be tested in a new way. Instead of varying the sense amp reference voltage, as in prior art signal margin tests, cell signal margin is tested by varying cell signal. The cell signal may be selected to determine both a high and a low signal margin.

公开(公告)号：GB2355327A

公开(公告)日：2001-04-18

申请号：GB0017095

申请日：2000-07-13

Applicant: IBM

Inventor： KIRIHATA TOSHIAKI ,  STORASKA DANIEL ,  NARAYAN CHANDRASEKHAR ,  TONTI WILLIAM ,  BERTIN CLAUDE ,  VAN HEEL NICK

IPC: G11C14/00 ,  G11C11/00 ,  G11C16/02 ,  G11C16/04 ,  G11C29/04 ,  H01L21/8246 ,  H01L27/112

Abstract: A Partially Non-Volatile Dynamic Random Access Memory (PNDRAM) uses a DRAM array formed by a plurality of single transistor (1T) cells or two transistor (2T) cells. The cells are electrically programmable as a non-volatile memory. This results in a single chip design featuring both, a dynamic random access memory (DRAM) and an electrically programmable-read-only-memory (EPROM). The DRAM and the EPROM integrated in the PNDRAM can be easily reconfigured at any time, whether during manufacturing or in the field. The PNDRAM has multiple applications such as combining a main memory with ID, BIOS, or operating system information in a single chip. Each cell includes a capacitor which permanently stores a 1 by breakdown of the capacitor when the cell acts as an EPROM cell.

公开(公告)号：GB2352855A

公开(公告)日：2001-02-07

申请号：GB0009818

申请日：2000-04-25

Applicant: IBM ,  SIEMENS AG

Inventor： KIRIHATA TOSHIAKI ,  MUELLER GERHARD

IPC: G11C11/401 ,  G11C16/06 ,  G11C29/00 ,  G11C29/04 ,  H01L21/82 ,  H01L21/8242 ,  H01L27/04 ,  H01L27/108 ,  G06F11/20

Abstract: A semiconductor integrated circuit device includes a redundant metal line 2 for replacing a non- operational metal line 4 for connecting to a circuit block 5. A spare circuit block is not needed. The redundant metal lines may be used in multiple levels of hierarchy within an integrated circuit device.

公开(公告)号：DE69125542D1

公开(公告)日：1997-05-15

申请号：DE69125542

申请日：1991-07-26

Applicant: IBM

Inventor： KATAYAMA YASUNAO ,  KIRIHATA TOSHIAKI ,  SCHEUERLEIN ROY E

IPC: G11C11/409 ,  G11C11/4091

Abstract: A dynamic random access memory comprises a sense amplifier including a latch (10) comprising a pair of NMOS FETs (TN1,TN2) with their gates and drains cross coupled and with their sources connected to a common node. A pair of bitlines (BL,BLN) are coupled to the cross coupled nodes of the latch (10). An FET (TP5) enables the bitlines to be precharged to a precharge voltage. A latch driving circuit (16) is coupled to the common node of the latch (10). The latch driving circuit (16) comprises means (TN5,TN6) for coupling a reference voltage to the common node for activating the latch (10) after the bitlines have been precharged, and means (TN7,20) for controlling the voltage of the common node in such a manner that the downward voltage swing of the lower level bitline towards the reference voltage, produced by activation of the latch (10), is limited to a predetermined voltage level higher than the reference voltage. This advantageously provides a high speed memory operation and reduced power consumption.

公开(公告)号：GB2508761B

公开(公告)日：2014-11-19

申请号：GB201404456

申请日：2012-09-13

Applicant: IBM

Inventor： FAINSTEIN DANIEL ,  CESTERO ALBERTO ,  IYER SUBRAMANIAN S ,  KIRIHATA TOSHIAKI

IPC: G11C29/00 ,  G06F21/44 ,  G06F21/73

Abstract: A random intrinsic chip ID generation employs a retention fail signature. A 1st and 2nd ID are generated using testing settings with a 1st setting more restrictive than the 2nd, creating more fails in the 1st ID bit string that includes 2nd ID bit string. A retention pause time controls the number of retention fails, adjusted by a BIST engine, wherein the fail numbers satisfy a predetermined fail target. Verification confirms whether the 1st ID includes the 2nd ID bit string, the ID being the one used for authentication. Authentication is enabled by a 3rd ID with intermediate condition such that 1st ID includes 3rd ID bit string and 3rd ID includes 2nd ID bit string. The intermediate condition includes a guard-band to eliminate bit instability problem near the 1st and 2nd ID boundary. The intermediate condition is changed at each ID read operation, resulting in a more secure identification.

公开(公告)号：GB2508761A

公开(公告)日：2014-06-11

申请号：GB201404456

申请日：2012-09-13

Applicant: IBM

Inventor： FAINSTEIN DANIEL ,  CESTERO ALBERTO ,  IYER SUBRAMANIAN S ,  KIRIHATA TOSHIAKI

IPC: G11C29/00 ,  G06F21/44 ,  G06F21/73

Abstract: A random intrinsic chip ID generation employs a retention fail signature. A 1st and 2nd ID are generated using testing settings with a 1st setting more restrictive than the 2nd, creating more fails in the 1st ID bit string 275 that includes 2nd ID bit string 290. A retention pause time controls the number of retention fails, adjusted by a BIST engine 625, wherein the fail numbers 803, 920 satisfy a predetermined fail target. Verification confirms whether the 1st ID includes the 2nd ID bit string, the ID being the one used for authentication. Authentication is enabled by a 3rd ID with intermediate condition such that 1st ID includes 3rd ID bit string and 3rd ID includes 2nd ID bit string. The intermediate condition includes a guard-band to eliminate bit instability problem near the 1st and 2nd ID boundary. The intermediate condition is changed at each ID read operation, resulting in a more secure identification.

公开(公告)号：DE602004026204D1

公开(公告)日：2010-05-06

申请号：DE602004026204

申请日：2004-08-25

Applicant: IBM

Inventor： KIRIHATA TOSHIAKI

IPC: G11C7/00 ,  G11C7/12 ,  G11C7/14 ,  G11C11/405 ,  G11C11/4094 ,  G11C11/4099