公开(公告)号：WO2010090781A3

公开(公告)日：2010-08-12

申请号：PCT/US2010/020098

申请日：2010-01-05

Applicant: ASM AMERICA, INC.

Inventor： REED, Joseph, C. ,  SHERO, Eric

IPC: H01L21/02 ,  H01L21/205

Abstract: A semiconductor processing apparatus includes a reaction chamber, a loading chamber, a movable support, a drive mechanism, and a control system. The reaction chamber includes a baseplate. The baseplate includes an opening. The movable support is configured to hold a workpiece. The drive mechanism is configured to move a workpiece held on the support towards the opening of the baseplate into a processing position. The control system is configured to create a positive pressure gradient between the reaction chamber and the loading chamber while the workpiece support is in motion. Purge gases flow from the reaction chamber into the loading chamber while the workpiece support is in motion. The control system is configured to create a negative pressure gradient between the reaction chamber and the loading chamber while the workpiece is being processed. Purge gases can flow from the loading chamber into the reaction chamber while the workpiece support is in the processing position, unless the reaction chamber is sealed from the loading chamber in the processing position.

公开(公告)号：WO2010080252A1

公开(公告)日：2010-07-15

申请号：PCT/US2009/066510

申请日：2009-12-03

Applicant: ASM AMERICA, INC.

Inventor： WHITE, Carl, L. ,  SHERO, Eric ,  REED, Joe

IPC: H01L21/205

CPC classification number: C23C16/45544 ,  C23C16/4585 ,  H01L21/67011 ,  H01L21/6719 ,  H01L21/68735 ,  H01L21/68771

Abstract: A semiconductor processing apparatus includes a reaction chamber (202, 302, 402), a movable susceptor (208, 308, 408, 508, 808), a movement element (210, 310, 810), and a control system (211, 811). The reaction chamber (202, 302, 402) includes a baseplate (212, 312, 412, 512, 812). The baseplate (212, 312, 412, 512, 812) includes an opening (250, 350, 450, 550). The movable susceptor (208, 308, 408, 508, 808) is configured to hold a workpiece (W). The movable element (210, 310, 810) is configured to move a workpiece (W) held on the susceptor (208, 308, 408, 508, 808) towards the opening (250, 350, 450, 550) of the baseplate (212, 312, 412, 512, 812). The control system (211, 811) is configured to space the susceptor (208, 308, 408, 508, 808) from the baseplate (212, 312, 412, 512, 812) by an unsealed gap (216, 316, 416, 516, 816) during processing of a workpiece (W) in the reaction chamber (202, 302, 402). Purge gases may flow through the gap (216, 316, 416, 516, 816) into the reaction chamber (202, 302, 402). Methods of maintaining the gap (216, 316, 416, 516, 816) during processing include calibrating the height of pads (520, 530) and capacitance measurements when the susceptor (208, 308, 408, 508, 808) is spaced from the baseplate (212, 312, 412, 512, 812).

Abstract translation: 半导体处理装置包括反应室（202,302,402），可移动基座（208,308,408,508,808），运动元件（210,310,810）和控制系统（211,811） ）。 反应室（202,302,402）包括基板（212,312,412,512,812）。 底板（212,312,412,512,812）包括开口（250,350,450,550）。 移动基座（208,308,408,508,808）构造成保持工件（W）。 可移动元件（210,310,810）被构造成将保持在基座（208,308,408,508,808a）上的工件（W）朝基板的开口（250,350,450,550）移动 212,312,412,512,812）。 控制系统（211,811）被配置为通过未密封的间隙（216,316,416,812）将基座（208,308,408,508,808）从底板（212,312,412,512,812） 516）在处理反应室（202,302,402）中的工件（W）时， 吹扫气体可以流过间隙（216,316,416,516,816）进入反应室（202,302,402）。 在处理过程中保持间隙（216,316,416,516,816）的方法包括：当基座（208,308,408,508,808）与第一和第二基板间隔开时，校准焊盘（520,530）的高度和电容测量值 底板（212,312,412,512,812）。

公开(公告)号：WO2010016964A2

公开(公告)日：2010-02-11

申请号：PCT/US2009/044734

申请日：2009-05-20

Applicant: ASM AMERICA, INC.

Inventor： AGGARWAL, Ravinder ,  HARO, Bob

IPC: H01L21/683 ,  H01L21/687

CPC classification number: C23C16/4585 ,  C23C16/46

Abstract: A one-piece susceptor ring for housing at least one temperature measuring device is provided. The susceptor ring includes a plate having an aperture formed therethrough and a pair of side ribs integrally connected to a lower surface of the plate. The side ribs are located on opposing sides of the aperture. The susceptor ring further includes a bore formed in each of the pair of side ribs. Each bore is configured to receive a temperature measuring device therein.

Abstract translation: 提供用于容纳至少一个温度测量装置的一体式基座环。 基座环包括具有穿过其形成的孔的板和与板的下表面一体连接的一对侧肋。 侧肋位于孔的相对侧上。 基座环还包括形成在一对侧肋中的每一个中的孔。 每个孔配置成在其中接收温度测量装置。

公开(公告)号：WO2009082539A1

公开(公告)日：2009-07-02

申请号：PCT/US2008/080810

申请日：2008-10-22

Applicant: ASM AMERICA, INC.

Inventor： AGGARWAL, Ravinder ,  KLESHOCK, Mark ,  JACOBS, Loren

IPC: G01K7/04 ,  G01K13/00 ,  G01K15/00 ,  H01L21/00

CPC classification number: G01K7/04 ,  G01K13/00 ,  G01K15/00 ,  H01L21/67248

Abstract: Systems are provided for measuring temperature in a semiconductor processing chamber. Embodiments provide a multi-junction thermocouple (110) comprising a first junction (112) and a second junction (114) positioned to measure temperature at substantially the same portion of a substrate (16). A controller (120) may detect failures in the first junction (112), the second junction (114), a first wire pair (113) extending from the first junction (112), or a second wire pair (115) extending from the second junction (114). The controller (120) desirably responds to a detected failure of the first junction (112) or first wire pair (113) by selecting the second junction (114) and second wire pair (115). Conversely, the controller (120) desirably responds to a detected failure of the second junction (114) or second wire pair (115) by selecting the first junction (112) and first wire pair (113). Systems taught herein may permit accurate and substantially uninterrupted temperature measurement despite failure of a junction or wire pair in a thermocouple.

Abstract translation: 提供用于测量半导体处理室中的温度的系统。 实施例提供了多结热电偶（110），其包括第一结（112）和第二结（114），第二结（114）被定位成测量衬底（16）的基本相同部分处的温度。 控制器（120）可以检测第一结（112），第二结（114），从第一结（112）延伸的第一线对（113）或从第一结（112）延伸的第二线对 第二结（114）。 控制器120期望通过选择第二连接点114和第二线对115来响应检测到的第一结112或第一线对113的故障。 相反地​​，控制器120期望通过选择第一结（112）和第一线对（113）来响应第二结（114）或第二线对（115）的检测到的故障。 尽管本文教导的系统可能允许精确和基本上不间断的温度测量，尽管热电偶中的接头或线对失效。

公开(公告)号：WO2009061599A1

公开(公告)日：2009-05-14

申请号：PCT/US2008/080198

申请日：2008-10-16

Applicant: ASM AMERICA, INC. ,  TOMASINI, Pierre ,  CODY, Nyles

Inventor： TOMASINI, Pierre ,  CODY, Nyles

IPC: C30B23/04 ,  C30B29/06 ,  C30B23/00 ,  C23C16/30 ,  C23C16/455 ,  H01L21/205 ,  H01L29/167

CPC classification number: H01L29/167 ,  C23C16/04 ,  C23C16/22 ,  C30B25/02 ,  C30B29/06 ,  H01L21/02381 ,  H01L21/02532 ,  H01L21/02579 ,  H01L21/0262 ,  H01L21/02636

Abstract: An embodiment provides a method for selectively depositing a single crystalline film. The method includes providing a substrate, which includes a first surface having a first surface morphology and a second surface having a second surface morphology different from the first surface morphology. A silicon precursor [108] and BCl 3 [134] are intermixed to thereby form a feed gas. The feed gas is introduced to the substrate under chemical vapor deposition conditions [122]. A Si-containing layer is selectively deposited onto the first surface without depositing on the second surface by introducing the feed gas [120].

Abstract translation: 一个实施方案提供了选择性沉积单晶膜的方法。 该方法包括提供基底，其包括具有第一表面形态的第一表面和具有不同于第一表面形态的第二表面形态的第二表面。 将硅前体108和BCl3 [134]混合，从而形成进料气体。 在化学气相沉积条件下，将进料气体引入基板[122]。 通过引入进料气体[120]，将含Si层选择性地沉积在第一表面上而不沉积在第二表面上。

公开(公告)号：WO2008042981A2

公开(公告)日：2008-04-10

申请号：PCT/US2007/080342

申请日：2007-10-03

Applicant: ASM AMERICA, INC. ,  WANG, Chang-gong ,  SHERO, Eric ,  WILK, Glen

Inventor： WANG, Chang-gong ,  SHERO, Eric ,  WILK, Glen

IPC: C23C16/40 ,  C23C16/455

CPC classification number: C23C16/405 ,  C23C16/401 ,  C23C16/45531

Abstract: Methods for forming metal silicate films are provided. The methods comprise contacting a substrate with alternating and sequential vapor phase pulses of a silicon source chemical, metal source chemical, and an oxidizing agent, wherein the metal source chemical is the next reactant provided after the silicon source chemical. Methods according to some embodiments can be used to form silicon-rich hafnium silicate and zirconium silicate films with substantially uniform film coverages on substrate surface.

Abstract translation: 提供了用于形成金属硅酸盐膜的方法。 该方法包括使衬底与硅源化学品，金属源化学品和氧化剂的交替和顺序汽相脉冲接触，其中金属源化学品是在硅源化学品之后提供的下一反应物。 根据一些实施方案的方法可以用于形成在基材表面上具有基本均匀的膜覆盖率的富硅硅酸铪和硅酸锆膜。

公开(公告)号：WO2008016748A1

公开(公告)日：2008-02-07

申请号：PCT/US2007/070796

申请日：2007-06-08

Applicant: ASM AMERICA, INC.

Inventor： LILJEROOS, Juha, Paul

IPC: H01L21/683

CPC classification number: H01L21/6838

Abstract: A Bernoulli wand (50) for transporting thin (e.g., 200 mm) semiconductor wafers (60) between a rack and a hot process chamber. The wand (50) has a head portion (54) that is configured to cover the entire wafer (60). The head (54) has a plurality of gas outlets (74) configured to produce a flow of gas along an upper surface of a wafer (60) to create a pressure differential between the upper surface (62) of the wafer (60) and the lower surface (68) of the wafer. The pressure differential generates a lift force that supports the wafer (60) below the head portion (54) of the wand (50) in a substantially non-contacting manner, employing the Bernoulli principle.

Abstract translation: 用于在机架和热处理室之间输送薄（例如200mm）半导体晶片（60）的伯努利棒（50）。 所述棒（50）具有构造成覆盖整个晶片（60）的头部（54）。 头部（54）具有多个气体出口（74），其构造成沿着晶片（60）的上表面产生气流，以在晶片（60）的上表面（62）和 晶片的下表面（68）。 压力差产生一种提升力，该升力以基本上非接触的方式使用伯努利原理支撑在杆（50）的头部（54）下方的晶片（60）。

公开(公告)号：WO2007024515A1

公开(公告)日：2007-03-01

申请号：PCT/US2006/031437

申请日：2006-08-14

Applicant: ASM AMERICA, INC. ,  PAGLIARO, JR., Robert, H.

Inventor： PAGLIARO, JR., Robert, H.

IPC: H01L21/02 ,  B08B3/12 ,  C02F9/00

CPC classification number: H01L21/02052 ,  Y10S438/906

Abstract: Methods are provided for producing a pristine hydrogen-terminated silicon wafer surface with high stability against oxidation. According to a step 20 of a process, the silicon wafer is treated with high purity, heated dilute hydrofluoric acid with anionic surfactant. In a subsequent step 30, the wafer is rinsed in-situ with ultrapure water at room temperature, and then dried in a subsequent drying step 40. Alternatively, the silicon wafer is treated with dilute hydrofluoric acid in step 22, rinsed with hydrogen gasified water in step 32, and dried in step 42. The silicon wafer produced by the method is stable in a normal clean room environment for greater than 3 days and has been demonstrated to last without significant oxide regrowth for greater than 8 days.

Abstract translation: 提供了用于生产具有高抗氧化稳定性的原始氢封端硅晶片表面的方法。 根据工艺的步骤20，用高纯度，加热的稀氢氟酸与阴离子表面活性剂处理硅晶片。 在随后的步骤30中，晶片在室温下用超纯水原位冲洗，然后在随后的干燥步骤40中干燥。或者，在步骤22中用稀氢氟酸处理硅晶片，用氢气化的水 在步骤32中，并在步骤42中干燥。通过该方法制备的硅晶片在正常的清洁室环境中稳定大于3天，并且已经证明在没有显着的氧化物再生长的情况下持续超过8天。

公开(公告)号：WO2006091510A1

公开(公告)日：2006-08-31

申请号：PCT/US2006/005868

申请日：2006-02-21

Applicant: ASM AMERICA, INC. ,  KUMAR, Davendra ,  GOUNDAR, Kamal, Kishore ,  KEMELING, Nathanael, R.C. ,  FUKUDA, Hideaki ,  SPREY, Hessel ,  STOKHOF, Maarten

Inventor： KUMAR, Davendra ,  GOUNDAR, Kamal, Kishore ,  KEMELING, Nathanael, R.C. ,  FUKUDA, Hideaki ,  SPREY, Hessel ,  STOKHOF, Maarten

IPC: H01L21/768 ,  H01L21/285

CPC classification number: H01L21/02063 ,  C23C14/02 ,  C23C16/02 ,  C23C16/36 ,  C23C16/45525 ,  C23C16/45531 ,  H01L21/28562 ,  H01L21/3105 ,  H01L21/76807 ,  H01L21/7681 ,  H01L21/76826 ,  H01L21/76831 ,  H01L21/76843 ,  H01L21/76846 ,  H01L21/76873

Abstract: Method and structures are provided for conformal lining of dual damascene structures in integrated circuits. Preferred embodiments are directed to providing conformal lining over openings formed in porous materials. Trenches are formed (100) in insulating layers. The layers are then adequately treated with a particular plasma process (101). Following this plasma treatment a self-limiting, self-saturating atomic layer deposition (ALD) reaction (115) can occur without significantly filling the pores forming improved interconnects.

Abstract translation: 提供了集成电路中双镶嵌结构的保形衬里的方法和结构。 优选实施例涉及在多孔材料中形成的开口上提供适形衬里。 在绝缘层中形成沟槽（100）。 然后用特定的等离子体处理（101）充分处理各层。 在这种等离子体处理之后，可以发生自限制的自饱和原子层沉积（ALD）反应（115）而不显着填充形成改进的互连的孔。

公开(公告)号：WO2006083821A1

公开(公告)日：2006-08-10

申请号：PCT/US2006/003333

申请日：2006-01-31

Applicant: ASM AMERICA, INC. ,  BAUER, Matthias ,  ARENA, Chantal ,  BERTRAM, Ronald ,  TOMASINI, Pierre ,  CODY, Nyles ,  BRABANT, Paul ,  ITALIANO, Joseph ,  JACOBSON, Paul ,  WEEKS, Keith, Doran

Inventor： BAUER, Matthias ,  ARENA, Chantal ,  BERTRAM, Ronald ,  TOMASINI, Pierre ,  CODY, Nyles ,  BRABANT, Paul ,  ITALIANO, Joseph ,  JACOBSON, Paul ,  WEEKS, Keith, Doran

IPC: C30B29/06 ,  C30B25/02 ,  C23C16/24 ,  H01L29/10 ,  H01L21/205 ,  C23C16/448

CPC classification number: H01L29/7848 ,  C23C16/04 ,  C23C16/22 ,  C23C16/24 ,  C23C16/32 ,  C23C16/325 ,  C23C16/45512 ,  C30B25/02 ,  C30B29/06 ,  H01L21/02381 ,  H01L21/02529 ,  H01L21/02532 ,  H01L21/02576 ,  H01L21/02579 ,  H01L21/0262 ,  H01L21/02636 ,  H01L21/02639 ,  H01L21/32056 ,  H01L21/3215 ,  H01L29/165 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/7834

Abstract: Chemical vapor deposition methods use trisilane and a halogen-containing etchant source (such as chlorine) to selectively deposit Si-containing films over selected regions of mixed substrates. Dopant sources may be intermixed with the trisilane and the etchant source to selectively deposit doped Si-containing films. The selective deposition methods are useful in a variety of applications, such as semiconductor manufacturing.

Abstract translation: 化学气相沉积方法使用丙硅烷和含卤素蚀刻剂源（例如氯）在混合基底的选定区域上选择性沉积含Si膜。 掺杂源可以与丙硅烷和蚀刻剂源混合以选择性沉积掺杂的含Si薄膜。 选择性沉积方法可用于各种应用，例如半导体制造。