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公开(公告)号：KR100782402B1
公开(公告)日：2007-12-07
申请号：KR1020060103455
申请日：2006-10-24
Applicant: 삼성전기주식회사
IPC: H05K3/20
CPC classification number: H05K3/205 , H05K1/11 , H05K3/3457 , H05K3/4007 , H05K2201/0394
Abstract: A printed circuit board and its manufacturing method are provided to implement a fine pattern by forming a circuit with a seed layer through an additive method. A method for manufacturing a printed circuit board includes the steps of: forming a first circuit pattern and a first pump protruded from the first circuit pattern on a carrier plate(S10); burying the first circuit pattern and the first bump on one side of an insulation substrate by pressing the carrier plate on the insulation substrate(S20); and forming a second circuit pattern electrically connected to the first bump on the other side of the insulation substrate(S30).
Abstract translation: 提供一种印刷电路板及其制造方法，以通过添加方法形成具有种子层的电路来实现精细图案。 一种制造印刷电路板的方法包括以下步骤：在载板上形成从第一电路图形突出的第一电路图案和第一泵; 通过将绝缘基板上的承载板压在绝缘基板的一侧上来掩埋第一电路图案和第一凸块（S20）; 以及形成与所述绝缘基板的另一侧上的所述第一凸块电连接的第二电路图案（S30）。
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公开(公告)号：KR100782407B1
公开(公告)日：2007-12-05
申请号：KR1020060105924
申请日：2006-10-30
Applicant: 삼성전기주식회사
IPC: H05K3/20
CPC classification number: H05K3/20 , H05K3/0058 , H05K3/108 , H05K3/4611 , H05K3/4682 , H05K2201/0394 , H05K2201/09481 , H05K2201/09518 , H05K2201/09563 , H05K2203/0152 , H05K2203/0376 , Y10T29/49126 , Y10T29/49128 , Y10T29/49155 , Y10T29/49156
Abstract: A method for manufacturing a circuit board is provided to reduce the whole thickness of a substrate by embedding a circuit pattern on the substrate and transferring a thin insulation layer on the substrate. A method for manufacturing a circuit board includes the steps of: forming a first circuit pattern on an insulation layer of a carrier on which the insulation layer and a first seed layer are sequentially stacked(S100); stacking one side of the carrier having the first circuit pattern to face an insulation substrate and compressing the carrier and the insulation substrate(S200); removing the carrier to transfer the first circuit pattern and the insulation layer on the insulation substrate(S300); and forming a second circuit pattern on the insulation layer transferred on the insulation substrate(S400).
Abstract translation: 提供一种制造电路板的方法，通过将电路图案嵌入衬底并在衬底上传输薄绝缘层来减小衬底的整体厚度。 一种制造电路板的方法包括以下步骤：在绝缘层和第一种子层依次层叠的载体的绝缘层上形成第一电路图案（S100）; 堆叠具有第一电路图案的载体的一侧面对绝缘基板并压缩载体和绝缘基板（S200）; 移除载体以将第一电路图案和绝缘层转移到绝缘基板上（S300）; 以及在绝缘层上转移的绝缘层上形成第二电路图案（S400）。
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公开(公告)号：KR100773331B1
公开(公告)日：2007-11-05
申请号：KR1020060028330
申请日：2006-03-29
Applicant: 삼성전기주식회사
IPC: H01L23/12
CPC classification number: H01L2224/81
Abstract: 플립칩 접속용 기판 및 그 제조방법이 개시된다. (a) 절연층을 포함하는 코어기판에, 시드층(seed layer)의 표면에 회로패턴이 형성되어 있는 매립(buried)패턴 기판을, 회로패턴이 코어기판에 대향하도록 적층하는 단계, (b) 시드층, 또는 시드층 및 코어기판의 일부를 천공하여 비아홀을 형성하는 단계, (c) 비아홀에 도전성 페이스트를 충전하는 단계, 및 (d) 시드층을 제거하는 단계를 포함하는 플립칩 접속용 기판 제조방법은, 플립칩 접속용 패드의 크기 및 돌출 높이를 용이하고 저렴하게 조절할 수 있고, 회로패턴이 절연재에 매립되어 있기 때문에 미세회로에서 발생하는 일종의 단락 현상인 소위 'copper migration'을 방지하는 데에 유리하며, 기판의 표면이 매끄럽게 형성되므로 플립칩 실장 후 충전되는 언더필 수지의 주입이 원활하고, 플립칩 뿐만 아니라 수동소자도 동시에 실장할 수 있으며, 페리페럴(peripheral) 타입 뿐만 아니라 어레이(array) 타입의 플립칩의 실장에도 용이하게 대응할 수 있고, 비아홀 내에 도전성 페이스트를 충전하므로 종래 방식에 비해 동도금 두께를 얇게 할 수 있어 동도금 시간을 단축할 수 있다.
플립칩, 시드층, 매립 회로패턴-
Patent Agency Ranking
公开(公告)号：KR100771467B1
公开(公告)日：2007-10-30
申请号：KR1020060105923
申请日：2006-10-30
Applicant: 삼성전기주식회사
IPC: H05K1/02
CPC classification number: H05K3/205 , H01L21/4846 , H01L23/49816 , H01L2224/16225 , H01L2224/16227 , H01L2224/73204 , H01L2924/15311 , H05K3/4007 , H05K2201/09745 , H05K2201/10674 , H05K2203/0338 , H05K2203/0435 , Y10T29/49126 , Y10T29/49128 , Y10T29/49144 , Y10T29/49149 , Y10T29/49155 , Y10T29/49165
Abstract: A circuit board and a manufacturing method thereof are provided to reduce the entire thickness of a package by condensing a solder in a substrate and to adjust an amount of a solder. A circuit board includes an insulation material(16), a circuit layer(24), a solder pad(20), and a circuit pattern(26). The insulation material includes a groove thereon. The circuit layer fills a portion of the grooves. The solder pad is formed on the circuit layer to fill the rest grooves. The circuit pattern is electrically connected to the circuit layer. A portion of the circuit pattern is buried by the insulation material such that the circuit pattern is exposed from a surface of the insulation material. The circuit patterns are buried on both sides of the insulation material. A metal film is applied between the circuit layer and the solder pad.
Abstract translation: 提供一种电路板及其制造方法，通过将衬底中的焊料冷凝并调整焊料的量来减小封装的整体厚度。 电路板包括绝缘材料（16），电路层（24），焊盘（20）和电路图案（26）。 绝缘材料在其上包括凹槽。 电路层填充一部分凹槽。 焊盘形成在电路层上以填充其余的沟槽。 电路图案电连接到电路层。 电路图案的一部分被绝缘材料掩埋，使得电路图案从绝缘材料的表面露出。 电路图案埋在绝缘材料的两侧。 在电路层和焊盘之间施加金属膜。
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公开(公告)号：KR100757910B1
公开(公告)日：2007-09-11
申请号：KR1020060063637
申请日：2006-07-06
Applicant: 삼성전기주식회사
IPC: H05K3/42
CPC classification number: H05K3/205 , H05K3/4038 , H05K3/4617 , H05K2203/0733 , H05K2203/1572
Abstract: A buried pattern substrate and a method for manufacturing the same are provided to reduce the thickness of the substrate by burying a circuit substrate in an insulating layer. A method for manufacturing a buried pattern substrate includes the steps of: laminating a first photo resist on a seed layer of a carrier film where the seed layer is laminated on a surface and selectively removing a part of the first photo resist by corresponding to a circuit pattern(102); forming the circuit pattern by depositing a coating layer on the seed layer(104); laminating a second photo resist to cover the circuit pattern and the first photo resist and selectively removing a part of the second photo resist by corresponding to a position where a stud bump is formed(106); depositing the coating layer on a part of the circuit pattern to form the stud bump by applying power to the seed layer(108); removing the first and second photo resists(110); laminating the carrier film on an insulating layer to pressurize the carrier film by making the circuit pattern and the stud bump facing the insulating layer(120); and removing the carrier film and the seed layer(130).
Abstract translation: 提供掩埋图案基板及其制造方法，以通过将电路基板埋入绝缘层来减小基板的厚度。 掩埋图形衬底的制造方法包括以下步骤：在载体膜的种子层上层叠第一光致抗蚀剂，其中晶种层层压在表面上，并且通过对应于电路选择性地去除第一光致抗蚀剂的一部分 图案（102）; 通过在种子层（104）上沉积涂层形成电路图案; 层叠第二光致抗蚀剂以覆盖电路图案和第一光刻胶，并且通过对应于形成有柱形凸起的位置（106）选择性地去除第二光致抗蚀剂的一部分; 通过向所述种子层（108）施加电力，将所述涂层沉积在所述电路图案的一部分上以形成所述凸起凸块; 去除所述第一和第二光致抗蚀剂（110）; 将所述载体膜层压在绝缘层上，以通过使所述电路图案和所述柱状凸起面向所述绝缘层（120）来对所述载体膜加压; 以及去除载体膜和种子层（130）。
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公开(公告)号：KR100735466B1
公开(公告)日：2007-07-03
申请号：KR1020060062943
申请日：2006-07-05
Applicant: 삼성전기주식회사
IPC: H05B41/26 , G02F1/13357
CPC classification number: H05B41/2827 , H05B41/3927
Abstract: A back-light inverter having a current detection function of an induction type is provided to maintain a uniform luminance by controlling a lamp current stably and uniformly. A back-light inverter having a current detection function of an induction type includes a driving unit(100), a main transformer(200), a sub transformer(300), a full wave rectifying unit(400), and a driving control unit(500). The driving unit(100) generates a first voltage controlled by a PWM scheme. The main transformer(200) has first and second coils, and converts the first voltage of the driving unit(100) into a second voltage according to a winding ratio of the first and second coils. The main transformer(200) outputs an AC driving current according to the second voltage to a lamp having both ends connected to both ends of the second coil. The sub transformer(300) has a first sub coil which is formed on a current line between the lamp and the second coil of the main transformer(200), and a second sub coil which is induced to the first sub coil. The sub transformer(300) detects a current which flows on the lamp according to a winding ratio of the first and second sub coils. The full wave rectifying unit(400) full-wave-rectifies the current detected by the sub transformer(300). The driving control unit(500) controls a PWM duty of the first voltage based on a voltage from the full wave rectifying unit(400).
Abstract translation: 提供具有感应型电流检测功能的背光逆变器，以通过稳定和均匀地控制灯电流来保持均匀的亮度。 具有感应型电流检测功能的背光逆变器包括驱动单元（100），主变压器（200），副变压器（300），全波整流单元（400）和驱动控制单元 （500）。 驱动单元（100）产生由PWM方案控制的第一电压。 主变压器（200）具有第一和第二线圈，并且根据第一和第二线圈的绕组比将驱动单元（100）的第一电压转换成第二电压。 主变压器（200）根据第二电压将AC驱动电流输出到两端连接到第二线圈两端的灯。 副变压器（300）具有形成在主变压器（200）的灯和第二线圈之间的电流线上的第一子线圈和被感应到第一子线圈的第二子线圈。 副变压器（300）根据第一和第二副线圈的绕组比来检测在灯上流动的电流。 全波整流单元（400）对由副变压器（300）检测到的电流进行全波整流。 驱动控制单元（500）基于来自全波整流单元（400）的电压来控制第一电压的PWM占空比。
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公开(公告)号：KR100688702B1
公开(公告)日：2007-03-02
申请号：KR1020050123205
申请日：2005-12-14
Applicant: 삼성전기주식회사
IPC: H05K3/42
Abstract: A manufacturing method of a printed circuit board with a landless via hole is provided to improve reliability of electrical connection between a circuit pattern and a copper plating layer inside a through hole by forming the circuit pattern while filling the through hole with a photosensitive resist. A manufacturing method of a printed circuit board(200) with a landless via hole includes the steps of: forming a through hole(142) on a surface of a base substrate(140); plating the surface of the base substrate(140) including the inside of a through hole with a copper; applying a photosensitive resist on a copper-plated surface for filling the inside of the through hole; patterning the photosensitive resist according to a predetermined pattern to remain the photosensitive resist filled in the inside of the through hole; forming a predetermined pattern by etching a copper-plated layer by using the patterned photosensitive resist as a mask; and removing the photosensitive resist, wherein the predetermined pattern is a landless structure having no via hole upper land.
Abstract translation: 提供一种具有无覆层过孔的印刷电路板的制造方法，以通过在用光致抗蚀剂填充通孔的同时形成电路图案来提高电路图案与通孔内的铜镀层之间的电连接的可靠性。 一种具有无埋层通孔的印刷电路板（200）的制造方法，包括以下步骤：在基底基板（140）的表面上形成通孔（142）; 用铜覆盖包括通孔内部的基底基板（140）的表面; 在镀铜表面上施加光敏抗蚀剂以填充通孔的内部; 根据预定图案构图光敏抗蚀剂以保留填充在通孔内部的光敏抗蚀剂; 通过使用图案化的光敏抗蚀剂作为掩模通过蚀刻铜镀层来形成预定图案; 并去除所述光敏抗蚀剂，其中所述预定图案是不具有通孔上平台的无平面结构。
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