公开(公告)号：KR1020050064564A

公开(公告)日：2005-06-29

申请号：KR1020030096035

申请日：2003-12-24

Applicant: 한국전자통신연구원

Inventor： 양일석 ,  김종대 ,  이대우 ,  노태문 ,  박일용 ,  권성구 ,  유병곤

IPC: G09G3/30

CPC classification number: G09G3/30 ,  G09G2310/027 ,  G09G2320/0276

Abstract: 본 발명은 디지털 신호를 아날로그 신호로 변환하고 이 변환과정에서 동시에 램프 신호를 생성하는 디지털-아날로그 변환/램프 회로를 구비하는 능동 구동형 EL의 소스 구동회로를 제공한다. 이를 통해 온도나 문턱전압 변동에 무관하고 종래의 램프 회로를 사용하지 않을 수 있어 고집적도가 가능하도록 할 수 있다.

公开(公告)号：KR100466540B1

公开(公告)日：2005-01-15

申请号：KR1020020051029

申请日：2002-08-28

Applicant: 한국전자통신연구원

Inventor： 양일석 ,  김종대 ,  노태문 ,  구진근 ,  이대우 ,  김상기 ,  박일용

IPC: H03K19/00

CPC classification number: H03K19/0016

Abstract: The present invention relates to an input and output port circuit. The input and output port circuit comprises a signal register for storing output signals, an input/output register at which an input/output control signal for determining an input/output direction is stored, a plurality of control registers, a power supply switch circuit for selectively supplying a low voltage or a high voltage depending on a power mode control signal, a signal direction control circuit for determining the direction of the signal depending on a value of the signal register and a value of the input/output register, an output control circuit driven depending on the value of the control register and an output of the signal direction control circuit, and an output driving circuit for outputting the low voltage, the high voltage or the ground value depending on an output of the signal direction control circuit and an output of the output control circuit. The high voltage and the low voltage can be simultaneously driven using only a single output driving circuit and the single output driving circuit is constructed in multiple stages and is selectively driven by the output control register. Therefore, the power consumption can be saved.

Abstract translation: 输入和输出端口电路 输入和输出端口电路包括用于存储输出信号的信号寄存器，存储用于确定输入/输出方向的输入/输出控制信号的输入/输出寄存器，多个控制寄存器，用于电源开关电路 根据功率模式控制信号选择性地提供低电压或高电压;信号方向控制电路，用于根据信号寄存器的值和输入/输出寄存器的值来确定信号的方向;输出控制 电路根据控制寄存器的值和信号方向控制电路的输出进行驱动;以及输出驱动电路，用于根据信号方向控制电路的输出输出低电压，高电压或接地值，以及 输出控制电路的输出。 高电压和低电压可以仅使用单个输出驱动电路同时驱动，并且单个输出驱动电路构造为多个级并且由输出控制寄存器选择性地驱动。 因此，可以节省功耗。

公开(公告)号：KR1020040046176A

公开(公告)日：2004-06-05

申请号：KR1020020074015

申请日：2002-11-26

Applicant: 한국전자통신연구원

Inventor： 노태문 ,  권성구 ,  박일용 ,  양일석 ,  이대우 ,  김상기 ,  유병곤 ,  김종대

IPC: H01L21/205

Abstract: PURPOSE: An apparatus for manufacturing a semiconductor device and a manufacturing method of the semiconductor device using the same are provided to be capable of effectively forming an insulating layer at a low temperature. CONSTITUTION: An apparatus for manufacturing a semiconductor device is provided with a reaction furnace(20), a wafer support part(40) installed in the reaction furnace for supporting a wafer, a heating part(50) for heating the wafer, a power supply(55) for supplying power to the heating part, and a gas flow part(10) for flowing reaction gas. The apparatus for manufacturing a semiconductor device further includes a plasma generating part(200) for transforming the reaction gas supplied from the gas flow part into ion reticle and supplying the ion reticle into the reaction furnace, and an ion removing part(300) for controlling the excessive flow of the ion reticle into the reaction furnace.

Abstract translation: 目的：提供一种用于制造半导体器件的装置和使用其的半导体器件的制造方法，以能够在低温下有效地形成绝缘层。 构成：半导体装置的制造装置具备反应炉（20），安装在用于支撑晶片的反应炉内的晶片支撑部（40），加热晶片的加热部（50），电源 （55），用于向加热部供电;以及气流部（10），用于使反应气体流动。 本发明的半导体装置的制造装置还包括：等离子体产生部（200），用于将从气体流供给的反应气体变换为离子掩模版并将离子掩模版供给到反应炉中;以及离子去除部（300） 离子掩模版过度流入反应炉。

公开(公告)号：KR100399583B1

公开(公告)日：2003-09-26

申请号：KR1019990053515

申请日：1999-11-29

Applicant: 한국전자통신연구원

Inventor： 김종대 ,  김상기 ,  구진근 ,  남기수 ,  이대우 ,  노태문

IPC: H01L27/085

CPC classification number: H01L29/7813 ,  H01L29/0847 ,  H01L29/42368

Abstract: The present invention relates to a method of fabricating a vertical TI)MOS power device using sidewall spacers and a self-align technique and a TDMOS power device of the same. The TDMOS according to the present invention is fabricated using only 3 masks and a source is formed using the self-align technique to embody a highly integrated trench formation. During the process, ion implantation of high concentration into the bottom of the trench makes a thick oxide film grow on the bottom and the corner of the gate, so that electrical characteristic, specifically leakage current and breakdown voltage of the device can be improved. Also, process steps can be much decreased to lower process cost, high integration is possible, and reliability of the device can be improved.

Abstract translation: 本发明涉及一种使用侧壁间隔件和自对准技术以及TDMOS功率器件制造垂直TI功率器件的方法。 根据本发明的TDMOS仅使用3个掩模制造，并且使用自对准技术形成源以体现高度集成的沟槽形成。 在此过程中，高浓度的离子注入到沟槽的底部使得在栅极的底部和拐角处生长出厚的氧化膜，从而可以改善器件的电特性，特别是漏电流和击穿电压。 而且，可以大大减少工艺步骤以降低工艺成本，可以实现高度集成，并且可以提高装置的可靠性。

公开(公告)号：KR1020020054110A

公开(公告)日：2002-07-06

申请号：KR1020000082805

申请日：2000-12-27

Applicant: 한국전자통신연구원

Inventor： 김종대 ,  김상기 ,  구진근 ,  노태문 ,  이대우 ,  조경익

IPC: H01L29/78

CPC classification number: H01L29/7813 ,  H01L29/4232 ,  H01L29/4238

Abstract: PURPOSE: A trench gate power device using hydrogen annealing and self-aligned technology is provided to remarkably reduce fabricating cost, by using three masks of fabricating a trench gate power metal oxide semiconductor field effect transistor(MOSFET), and to improve on-resistance by forming a source while a sidewall oxide layer and the self-aligned technology are used. CONSTITUTION: A hydrogen annealing process is performed regarding a trench to round the corner portion of the trench so that a uniform oxide layer is grown on the trench to improve an electrical characteristic. The annealing process is performed by using a pull-back region which is generated by removing a trench sidewall oxide layer.

Abstract translation: 目的：通过使用制造沟槽栅极功率金属氧化物半导体场效应晶体管（MOSFET）的三个掩模，提供使用氢退火和自对准技术的沟槽栅极功率器件，以显着降低制造成本，并通过 在使用侧壁氧化物层和自对准技术的同时形成源极。 构成：对沟槽进行氢退火处理以使沟槽的拐角部分圆周化，使得在沟槽上生长均匀的氧化物层以改善电特性。 通过使用通过去除沟槽侧壁氧化物层产生的拉回区域来执行退火处理。

公开(公告)号：KR1020020049162A

公开(公告)日：2002-06-26

申请号：KR1020000078264

申请日：2000-12-19

Applicant: 한국전자통신연구원

Inventor： 노태문 ,  김종대 ,  김상기 ,  이대우 ,  구진근 ,  조경익

IPC: H01L27/04

Abstract: PURPOSE: A method for fabricating a power integrated circuit is provided to remarkably reduce a high temperature annealing process for fabricating the power integrated circuit, by mixing a non-reduced surface field(RESURF) n-lateral double diffused metal oxide semiconductor(LDMOS) transistor and a RESURF p-LDMOS transistor. CONSTITUTION: The power integrated circuit includes the RESURF LDMOS transistor using a silicon-on-insulator, the non-RESURF LDMOS transistor of an opposite type to the RESURF LDMOS transistor and a logic complementary metal oxide semiconductor(CMOS). The regions where the logic CMOS as a low voltage device and an LDMOS transistor as a high power device are fabricated are doped with the same impurity type in a silicon substrate.

Abstract translation: 目的：提供一种制造功率集成电路的方法，通过混合非还原表面场（RESURF）n侧双扩散金属氧化物半导体（LDMOS）晶体管，显着降低制造功率集成电路的高温退火工艺 和RESURF p-LDMOS晶体管。 构成：功率集成电路包括使用绝缘体上硅的RESURF LDMOS晶体管，与RESURF LDMOS晶体管相反类型的非RESURF LDMOS晶体管和逻辑互补金属氧化物半导体（CMOS）。 制造作为低电压器件的逻辑CMOS和作为高功率器件的LDMOS晶体管的区域在硅衬底中掺杂相同的杂质类型。

公开(公告)号：KR1020020043996A

公开(公告)日：2002-06-14

申请号：KR1020000073473

申请日：2000-12-05

Applicant: 한국전자통신연구원

Inventor： 구진근 ,  노태문 ,  이대우 ,  김상기 ,  김종대

IPC: H01L21/336

Abstract: PURPOSE: A method for fabricating a high-current power integrated circuit is provided to decrease the size of a high-current integrated circuit(IC) chip, by integrating a high-current trench gate DMOS power device and high-voltage lateral double diffused MOS(LDMOS) and complementary MOS(CMOS) devices in an n-type epitaxial layer on a p-type silicon substrate. CONSTITUTION: A thick thermal oxide layer is grown on the p-type silicon substrate(1) and a photolithography process is performed regarding the thermal oxide layer to define an n-type buried layer(2). The density of the n-type buried layer is controlled according to a breakdown voltage. Phosphorous ions are implanted into the n-type buried layer and are diffused in an oxidation atmosphere so that a phosphorous-doped n-type epitaxial layer is grown. An n-well and a p-well are formed, wherein a high temperature heat treatment process is performed to make the junction of the n-type buried layer out-diffused to a lower portion of a gate electrode. A trench device is isolated. A p-body junction is formed as a channel region of a trench gate DMOS. A field oxide layer region is defined and a field threshold voltage is controlled. An oxide layer is grown. A gate oxide layer of the high-voltage LDMOS and CMOS devices is grown, and a threshold voltage is controlled to form the gate electrode. An LDD junction is formed and a sidewall oxide layer(17) is formed. The source and drain of the CMOS and LDMOS trench gate DMOS devices are joined and a metal interconnection is formed.

Abstract translation: 目的：提供一种大电流功率集成电路的制造方法，通过集成高电流沟槽栅极DMOS功率器件和高电压侧向双扩散MOS（MOS）功率来减小大电流集成电路（IC）芯片的尺寸 （LDMOS）和互补MOS（CMOS）器件在p型硅衬底上的n型外延层中。 构成：在p型硅衬底（1）上生长厚的氧化物层，并且对热氧化层进行光刻工艺以限定n型掩埋层（2）。 n型掩埋层的密度根据击穿电压进行控制。 将磷离子注入到n型掩埋层中并在氧化气氛中扩散，从而生长磷掺杂的n型外延层。 形成n阱和p阱，其中进行高温热处理工艺以使n型掩埋层的结外扩散到栅电极的下部。 隔离沟槽装置。 p体结形成为沟槽栅DMOS的沟道区。 定义场氧化物层区域并控制场阈值电压。 生长氧化物层。 生长高压LDMOS和CMOS器件的栅极氧化层，并且控制阈值电压以形成栅电极。 形成LDD结，形成侧壁氧化物层（17）。 CMOS和LDMOS沟槽栅极DMOS器件的源极和漏极被连接并形成金属互连。

公开(公告)号：KR1020010048716A

公开(公告)日：2001-06-15

申请号：KR1019990053515

申请日：1999-11-29

Applicant: 한국전자통신연구원

Inventor： 김종대 ,  김상기 ,  구진근 ,  남기수 ,  이대우 ,  노태문

IPC: H01L27/085

CPC classification number: H01L29/7813 ,  H01L29/0847 ,  H01L29/42368

Abstract: PURPOSE: A method for manufacturing a trench gate power device using a self-aligned technology is provided to form a trench double diffused metal-oxide-semiconductor(TDMOS) power device by using only three masks wherein a trench sidewall layer and a self-aligned technique are utilized. CONSTITUTION: After an oxide layer and a nitride layer are sequentially grown on a silicon substrate, impurity ions are implanted by using the first mask to form a channel layer of a device. After a sidewall oxide layer and a trench are sequentially formed on the resultant structure, the sidewall oxide layer is eliminated to implant impurity ions into the bottom surface of the trench and into the region where the sidewall layer is eliminated. A gate oxide layer is grown on the surface of the trench. Polycrystalline silicon is filled inside the trench by using the second mask to form a gate electrode. An oxide layer is deposited on the trench, and an etch-back process is performed until the nitride layer is exposed. The nitride layer is removed. Impurity ions are implanted to form a body contact by using a self-aligned technology. An electrode for forming a terminal is formed on the resultant structure by using the third mask.

Abstract translation: 目的：提供一种使用自对准技术制造沟槽栅极功率器件的方法，以通过仅使用三个掩模形成沟槽双扩散金属氧化物半导体（TDMOS）功率器件，其中沟槽侧壁层和自对准 技术被利用。 构成：在硅衬底上依次生长氧化物层和氮化物层之后，通过使用第一掩模注入杂质离子以形成器件的沟道层。 在所得结构上顺序地形成侧壁氧化物层和沟槽之后，消除侧壁氧化物层，以将杂质离子注入到沟槽的底表面中，并进入去除侧壁层的区域。 栅极氧化层生长在沟槽表面上。 通过使用第二掩模将多晶硅填充在沟槽内部以形成栅电极。 在沟槽上沉积氧化物层，并且进行回蚀处理直至暴露氮化物层。 去除氮化物层。 通过使用自对准技术植入杂质离子以形成身体接触。 通过使用第三掩模，在所得结构上形成用于形成端子的电极。

公开(公告)号：KR100258177B1

公开(公告)日：2000-06-01

申请号：KR1019970072051

申请日：1997-12-22

Applicant: 한국전자통신연구원

Inventor： 노태문 ,  이대우 ,  김상기 ,  구진근 ,  남기수 ,  김종대

IPC: H01L27/04

Abstract: PURPOSE: A method for manufacturing a power device and a structure thereof are provided to improve the reliability of an integrated circuit by allowing the power device to be operated in a stable state. CONSTITUTION: A polycrystalline silicon layer(14) is formed on the first silicon substrate(11). The first silicon substrate(11) is made of active silicon. A diamond thin film layer(13) having a superior resistivity is formed on the polycrystalline silicon layer(14). The surface of the polycrystalline silicon layer(14) is polished by a chemical mechanical polishing process. An SOI(silicon on insulator) insulating layer(12) having a cylindrical hole is formed on the diamond thin film layer(13). The second silicon substrate(15) is formed on the SOI insulating layer(12). Various devices are formed on the second silicon substrate so as to form a power device.

Abstract translation: 目的：提供一种用于制造功率器件的方法及其结构，以通过允许电力设备在稳定状态下工作来提高集成电路的可靠性。 构成：在第一硅衬底（11）上形成多晶硅层（14）。 第一硅衬底（11）由有源硅制成。 在多晶硅层（14）上形成具有优异电阻率的金刚石薄膜层（13）。 通过化学机械抛光工艺抛光多晶硅层（14）的表面。 在金刚石薄膜层（13）上形成有具有圆柱形孔的SOI（绝缘体上硅）绝缘层（12）。 第二硅衬底（15）形成在SOI绝缘层（12）上。 在第二硅衬底上形成各种器件以形成功率器件。

公开(公告)号：KR1020000021964A

公开(公告)日：2000-04-25

申请号：KR1019980041256

申请日：1998-09-30

Applicant: 한국전자통신연구원

Inventor： 김종대 ,  김상기 ,  이대우 ,  구진근 ,  김대용

IPC: H01L29/772

Abstract: PURPOSE: A method of manufacturing a power device of a trench double diffused metal oxide(TDMOS) semiconductor is provided to increase the breakdown voltage and reduce the leakage current of the power device by forming a thick oxidation layer in the vicinity of the top and bottom of the trench gate. CONSTITUTION: A method of manufacturing a power device of a trench double diffused metal oxide(TDMOS) semiconductor comprises the steps of: forming a trench after etching an oxidation layer, a nitride layer and an oxidation layer on a substrate, and growing a second nitride layer; growing a first thick oxidation layer on the bottom of the trench by using reactive ion etching; growing a second thick oxidation layer after filling up the inside of the trench with a photoresist layer; eliminating the second thick oxidation layer after evaporating a polysilicon layer, and etching a first nitride layer; and forming a side wall space after eliminating the first nitride layer, and forming a metal electrode.

Abstract translation: 目的：提供一种制造沟槽双重扩散金属氧化物（TDMOS）半导体的功率器件的方法，以通过在顶部和底部附近形成厚的氧化层来增加击穿电压并降低功率器件的漏电流 的沟槽门。 构成：制造沟槽双重扩散金属氧化物（TDMOS）半导体的功率器件的方法包括以下步骤：在蚀刻氧化层，氮化物层和氧化层之后，在衬底上形成沟槽，并且生长第二氮化物 层; 通过使用反应离子蚀刻在沟槽的底部生长第一厚氧化层; 在用光致抗蚀剂层填充沟槽内部后生长第二厚氧化层; 在蒸发多晶硅层之后消除第二厚氧化层，并蚀刻第一氮化物层; 以及在消除第一氮化物层之后形成侧壁空间，并形成金属电极。