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    ELECTRONIC MODULE AND PACKAGING METHOD THEREOF
    121.
    发明公开
    ELECTRONIC MODULE AND PACKAGING METHOD THEREOF 审中-公开
    电子模块及其封装方法

    公开(公告)号：EP2447993A1

    公开(公告)日：2012-05-02

    申请号：EP10809474.9

    申请日：2010-05-07

    Applicant: Huawei Device Co., Ltd.

    Inventor： QIAO, Jitao

    IPC: H01L23/48 ,  H01L23/12 ,  H01L25/00

    CPC classification number: H01L23/49805 ,  H01L23/13 ,  H01L25/105 ,  H01L25/16 ,  H01L2924/15162 ,  H01L2924/15323 ,  H05K1/141 ,  H05K3/3436 ,  H05K3/3442 ,  H05K2201/09136 ,  H05K2201/10727

    Abstract: Embodiments of the present invention provide an electronic module and a packaging structure of the electronic module. The electronic module includes: a substrate; at least one electronic component, arranged on an upper surface of the substrate; and a first conductive part and a second conductive part, configured to connect the electronic module to an external printed circuit board; the first conductive part is arranged at a lower surface of the substrate and is electrically connected to the electronic component; and the second conductive part is arranged across a lateral surface of the substrate and the lower surface of the substrate. The electronic module is packaged with the printed circuit board by arranging a second conductive part across the lateral surface of the substrate and the lower surface of the substrate, which improves the quality of welding between the electronic module and the printed circuit board.

    SEMICONDUCTOR DEVICE
    122.
    发明公开
    SEMICONDUCTOR DEVICE 审中-公开
    半导体器件

    公开(公告)号：EP3261416A1

    公开(公告)日：2017-12-27

    申请号：EP17177033.2

    申请日：2017-06-21

    Applicant: JTEKT CORPORATION

    Inventor： TANI, Naoki

    IPC: H05K1/02 ,  H01L23/12

    CPC classification number: H01L23/49816 ,  H01L23/12 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/522 ,  H01L23/562 ,  H01L2224/16225 ,  H01L2224/73204 ,  H05K1/0271 ,  H05K2201/068 ,  H05K2201/09136 ,  H05K2201/10568 ,  H05K2201/2018

    Abstract: A semiconductor device 100 includes a semiconductor element 1, a circuit board 2, metal wires 3A to 3F, and an expanding member 5. The circuit board 2 has an upper surface 21 and a lower surface 22 opposite the upper surface 21. The metal wires 3A to 3F are formed on at least one of the upper surface 21 and the lower surface 22. At least two connection terminals are formed in a terminal formation surface 13 of the semiconductor element 1 which is disposed so as to face the upper surface 21 of the circuit board 2. The expanding member 5 is fixed to the terminal formation surface 13 of the semiconductor element 1, has a larger coefficient of linear thermal expansion than the semiconductor element 1, and has a size larger than the interval between adjacent two of the at least two connection terminals.

    Abstract translation: 半导体器件100包括半导体元件1，电路板2，金属线3A至3F以及扩展构件5.电路板2具有上表面21和与上表面21相对的下表面22.金属线 3A至3F形成在上表面21和下表面22中的至少一个上。至少两个连接端子形成在半导体元件1的端子形成表面13中，该端子形成表面13被布置成面向上表面21 电路基板2.扩张部件5固定在半导体元件1的端子形成面13上，线膨胀系数比半导体元件1大，其尺寸比相邻的两个 至少两个连接端子。

    LIGHT EMITTING APPARATUS AND ILLUMINATING APPARATUS
    125.
    发明公开
    LIGHT EMITTING APPARATUS AND ILLUMINATING APPARATUS 有权
    发光装置和照明装置

    公开(公告)号：EP2634480A1

    公开(公告)日：2013-09-04

    申请号：EP12834577.4

    申请日：2012-10-18

    Applicant: Panasonic Corporation

    Inventor： UENOYAMA, Koji ,  OOTUBO, Atusi ,  MATSUMOTO, Hiroyuki

    IPC: F21V29/00 ,  F21S2/00 ,  F21V19/00 ,  F21V23/00 ,  H01L33/00 ,  F21Y101/02

    CPC classification number: F21V29/004 ,  F21K9/23 ,  F21K9/27 ,  F21S8/04 ,  F21V3/00 ,  F21V29/508 ,  F21Y2103/33 ,  F21Y2105/10 ,  F21Y2115/10 ,  H05B33/0821 ,  H05K1/0201 ,  H05K1/0209 ,  H05K1/0271 ,  H05K1/181 ,  H05K2201/09136 ,  H05K2201/09781 ,  H05K2201/10106

    Abstract: A light-emitting device includes: a board (18); light-emitting elements (60a and 60b) interconnected in parallel and provided above a top face (65) of the board (18); light-emitting elements (60e and 60f), one of which is connected in series with the light-emitting element (60a) and the other of which is connected in series with the light-emitting element (60b), the light-emitting elements (60e and 60f) being interconnected in parallel; a metal pattern (67a) provided continuously under the light-emitting elements (60a and 60b), on an undersurface (28) of the board (18); and a metal pattern (67b) provided continuously under the light-emitting elements (60e and 60f), and isolated from the first metal pattern (67a).

    Abstract translation: 发光装置包括：板（18）; 发光元件（60a和60b），所述发光元件（60a和60b）平行互连并设置在所述板（18）的顶面（65）上方; 其中一个发光元件（60a和60f）与发光元件（60a）串联连接并且另一个与发光元件（60b）串联连接，发光元件 （60e和60f）并联连接; 在所述基板（18）的下表面（28）上，在所述发光元件（60a，60b）的下方连续设置的金属图案（67a）。 以及连续设置在发光元件（60e，60f）的下方且与第一金属图案（67a）隔离的金属图案（67b）。

    METHOD OF BALANCING MULTILAYER SUBSTRATE STRESS AND MULTILAYER SUBSTRATE
    127.
    发明公开
    METHOD OF BALANCING MULTILAYER SUBSTRATE STRESS AND MULTILAYER SUBSTRATE 有权
    平衡多层基板应力和多层基板的方法

    公开(公告)号：EP2270851A1

    公开(公告)日：2011-01-05

    申请号：EP08733855.4

    申请日：2008-03-31

    Applicant: Princo Corp.

    Inventor： YANG, Chih-kuang

    IPC: H01L23/12 ,  H05K1/02 ,  B32B9/00

    CPC classification number: H05K1/0271 ,  H05K1/0224 ,  H05K1/028 ,  H05K3/4611 ,  H05K3/4644 ,  H05K2201/0394 ,  H05K2201/09136 ,  H05K2201/0969 ,  H05K2201/09781

    Abstract: Disclosed is a method to decrease warpage of a multi-layer substrate, comprises a first metal layer and a second metal layer. First area of the first metal layer is larger than second area of the second metal layer. In the same layer of the second metal layer, a redundant metal layer can be set to make a redundant metal layer area plus the second area considerably equivalent to the first area. Alternatively, a redundant space can be set in the first metal layer to achieve the same result. When the multi-layer substrate comprises a first dielectric layer with an opening and a second dielectric layer, a redundant opening positioned corresponding to the opening can be set in the second dielectric layer. The present invention employs a method of balancing the multi-layer substrate stress, i.e. to homogenize the multi-layer structure composed of different metal layers and dielectric layers to decrease warpage thereof.

    Abstract translation: 公开了一种减少多层基板翘曲的方法，包括第一金属层和第二金属层。 第一金属层的第一面积大于第二金属层的第二面积。 在第二金属层的同一层中，可以设置冗余金属层以形成冗余金属层区域加上与第一区域相当的第二区域。 或者，可以在第一金属层中设置冗余空间以实现相同的结果。 当多层基板包括具有开口的第一电介质层和第二电介质层时，可以在第二电介质层中设置与开口对应的冗余开口。 本发明采用平衡多层衬底应力的方法，即均匀化由不同金属层和介电层组成的多层结构以减少其翘曲。

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