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公开(公告)号：KR1020130015063A
公开(公告)日：2013-02-13
申请号：KR1020110076873
申请日：2011-08-02
Applicant: 한국전자통신연구원
CPC classification number: H02M3/1582
Abstract: PURPOSE: A DC-DC converter for setting topology is provided to prevent the backflow of a current by controlling a switch unit through a signal of a backflow detecting unit. CONSTITUTION: A topology selecting unit(140) selects topology according to an external input signal and generates a signal corresponding to the selected topology. A pulse width modulating unit(150) generates a signal to determine the operation time of the switch unit. A backflow detecting unit(170) generates a signal by detecting the backflow of a current flowing in the switch unit. A switch control unit(160) controls the switch unit according to the signals of the backflow detecting unit, the pulse width modulating unit, and the topology selecting unit. [Reference numerals] (122) First short circuit unit; (124) Second short circuit unit; (126) Third short circuit unit; (128) Fourth short circuit unit; (140) Topology selecting unit; (150) Pulse width modulating unit; (160) Switch control unit; (172) First backflow detecting unit; (174) Second backflow detecting unit; (AA) Input; (BB) Output; (CC) Topology input
Abstract translation: 目的：提供用于设置拓扑的DC-DC转换器，以通过控制回流单元通过回流检测单元的信号来防止电流回流。 构成：拓扑选择单元（140）根据外部输入信号选择拓扑，并产生对应于所选拓扑的信号。 脉冲宽度调制单元（150）产生确定开关单元的操作时间的信号。 回流检测单元（170）通过检测在开关单元中流动的电流的回流来产生信号。 开关控制单元（160）根据回流检测单元，脉冲宽度调制单元和拓扑选择单元的信号控制开关单元。 （附图标记）（122）第一短路单元; （124）第二短路单元; （126）第三短路单元; （128）第四短路单元; （140）拓扑选择单元; （150）脉宽调制单元; （160）开关控制单元; （172）第一回流检测单元; （174）第二回流检测单元; （AA）输入; （BB）输出; （CC）拓扑输入
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公开(公告)号：KR101201893B1
公开(公告)日：2012-11-16
申请号：KR1020080131613
申请日：2008-12-22
Applicant: 한국전자통신연구원
CPC classification number: H03F3/45475 , H03F3/45968 , H03F2203/45212
Abstract: 본 발명은 고속 다단 전압 비교기에 관한 것으로, 본 발명에 따른 다단 전압 비교기는 옵셋 제거 스위치에 의해 각 전단 증폭기의 출력에서 옵셋을 제거할 수 있도록 구성되어 있으며, 아울러 리셋 스위치에 의해 각 전단 증폭기의 출력을 리셋시켜 출력 회복 시간을 감소시킬 수 있도록 구성되어 있다. 따라서, 본 발명에 따른 다단 전압 비교기는 높은 정확도를 가지면서 고속 동작이 가능하므로, 아날로그-디지털 변환기, 특히 고속 SAR ADC에 유용하게 적용이 가능하다.
고속, 다단, 비교기, 옵셋, 출력 회복 시간, 전단 증폭기, SAR ADC-
公开(公告)号：KR1020120118672A
公开(公告)日：2012-10-29
申请号：KR1020110036187
申请日：2011-04-19
Applicant: 한국전자통신연구원
IPC: H02P6/10
Abstract: PURPOSE: A motor control apparatus and a control method thereof are provided to reduce the operation quantity of a digital processor and to reduce the torque ripple of an electric motor. CONSTITUTION: A preprocessing unit(200) calculates counter-electromotive force from a three phase current signal or a three phase voltage signal. A control unit(300) drives the electric motor with reference to the counter-electromotive force. An offset compensating unit receives the current signal. The offset compensating unit compensates the offset of the received current signal. [Reference numerals] (100) Motor; (200) Preprocessing unit; (300) Control unit; (AA) Three-phase electric current signal; (BB) Three-phase voltage signal; (CC) Three-phase reverse electromotive force; (DD) Three-phase driving current; (EE) Motor control unit
Abstract translation: 目的：提供电动机控制装置及其控制方法，以减少数字处理器的操作量并减小电动机的转矩波动。 构成：预处理单元（200）从三相电流信号或三相电压信号计算反电动势。 控制单元（300）参照反电动势来驱动电动机。 偏移补偿单元接收电流信号。 偏移补偿单元补偿接收的电流信号的偏移。 （附图标记）（100）电机; （200）预处理单元; （300）控制单元; （AA）三相电流信号; （BB）三相电压信号; （CC）三相反向电动势; （DD）三相驱动电流; （EE）电机控制单元
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公开(公告)号：KR101182407B1
公开(公告)日：2012-09-13
申请号：KR1020080131642
申请日：2008-12-22
Applicant: 한국전자통신연구원
IPC: H03M3/02
CPC classification number: H03M3/372 , H03K3/3565 , H03M3/43 , H03M3/454
Abstract: 본 발명은 연속시간 시그마-델타 변조기에 사용되는 클럭 생성기에 대한 것으로서, 이 클럭 생성기는 인에이블 신호에 따라 발진하여 펄스를 생성하는 발진기, 상기 발진기의 펄스를 세어 누적된 펄스 수를 출력하는 계수기, 그리고 상기 계수기의 펄스수가 펄스폭조절값과 같아지면 비활성화된 출력신호를 출력하는 출력부를 포함하며, 상기 발진기는 비안정 멀티바이브레이터를 포함한다. 따라서, 지터가 있는 클럭으로부터 지터가 적은 펄스를 생성하는 비안정 멀티바이브레이터를 발진기로 사용함으로써 신호대잡음비 효율을 높이고, 디지털 회로만으로 구성되어 회로설계가 용이하고 펄스폭 조정이 용이하다. 또한 비안정 멀티바이브레이터의 구조에 따라 연속시간 시그마-델타 변조기에 사용된 저항과 커패시터 공정 변화와 연동되어 펄스폭이 조정되도록 설계가 가능하다.
비안정 멀티바이브레이터, 고정 펄스 폭, 연속 시간 시그마-델타, 아날로그-디지털변환기, 클럭 지터-
公开(公告)号：KR1020120066996A
公开(公告)日：2012-06-25
申请号：KR1020100128376
申请日：2010-12-15
Applicant: 한국전자통신연구원
CPC classification number: H03F3/45475 , H03F2203/45248 , H03F2203/45514 , H03F2203/45541 , H03F2203/45551 , H02M1/42
Abstract: PURPOSE: A bias circuit and an analog integrated circuit including the same are provided to improve a slew rate by preventing power consumption from increasing. CONSTITUTION: A reference current source unit(211) provides a current source to a dynamic bias circuit(210). A source follower unit(212) receives a first amplifier input signal and a second amplifier input signal. The voltage difference of the first amplifier input signal and the second amplifier input signal is propositional to the voltage difference of a first input signal and a second input signal. A current control unit(213) includes a first branch(213_1) and a second branch(213_2). The current control unit provides a variable current to a bias voltage generation unit(214). The bias voltage generation unit receives a reference current from the reference current source unit. The bias voltage generation unit receives the variable current from the current control unit.
Abstract translation: 目的：提供偏置电路和包括该偏置电路的模拟集成电路，以通过防止功耗增加来提高转换速率。 构成：参考电流源单元（211）向动态偏置电路（210）提供电流源。 源跟随器单元（212）接收第一放大器输入信号和第二放大器输入信号。 第一放大器输入信号和第二放大器输入信号的电压差与第一输入信号和第二输入信号的电压差有关。 电流控制单元（213）包括第一分支（213_1）和第二分支（213_2）。 电流控制单元向偏置电压产生单元（214）提供可变电流。 偏置电压产生单元从参考电流源单元接收参考电流。 偏置电压产生单元从电流控制单元接收可变电流。
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Patent Agency Ranking
公开(公告)号：KR1020120064505A
公开(公告)日：2012-06-19
申请号：KR1020100125775
申请日：2010-12-09
Applicant: 한국전자통신연구원
CPC classification number: H03M1/069 , H03M1/168 , H03M1/12 , H03M13/6502
Abstract: PURPOSE: A pipelined ADC(Analog To Digital Converter) is provided to simply perform a logical correction operation by performing a binary shift when data errors are corrected. CONSTITUTION: A conversion stage circuit(1100) includes a plurality of conversion stages(1110-11K0) which is serially connected. The conversion stage converts inputted voltages into B bits of digital codes. The conversion stage outputs residual voltages to a rear end. A digital correction circuit(1200) performs a shift operation and a logic correcting operation by adding a predetermined value to digital codes outputted from the conversion stage circuit. A clock signal generator(1300) generates clock signals necessary for a conversion operation by receiving clock voltages. A reference voltage buffer(1400) generates reference voltages necessary for the conversion operation.
Abstract translation: 目的：提供流水线ADC（模拟到数字转换器），以便在纠正数据错误时执行二进制移位来简单执行逻辑校正操作。 构成：转换级电路（1100）包括串联连接的多个转换级（1110-11K0）。 转换级将输入的电压转换成B位的数字代码。 转换级将剩余电压输出到后端。 数字校正电路（1200）通过向从转换级电路输出的数字代码添加预定值来执行移位操作和逻辑校正操作。 时钟信号发生器（1300）通过接收时钟电压产生转换操作所需的时钟信号。 参考电压缓冲器（1400）产生转换操作所需的参考电压。
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公开(公告)号：KR1020120041941A
公开(公告)日：2012-05-03
申请号：KR1020100103365
申请日：2010-10-22
Applicant: 한국전자통신연구원
Abstract: PURPOSE: An apparatus for adjusting clock timing and a modulator for continuous time delta-sigma using the same are provided to compensate the time delay of a CT(Continuous Time)-integrator and a DAC(Digital Analog Converter) by adjusting the time difference of a DAC clock and a quantizer clock. CONSTITUTION: A power detecting unit(110) detects the power of input signals respectively corresponding to two or more clock time differences. The power detected from the input signal is proportional to energy having a noise transfer characteristic. The power detecting unit determines the noise transfer characteristic of an input signal. The power detecting unit generates a control signal specifying the clock time difference of detected minimum power. A timing control unit(120) receives a reference clock and the control signal. The timing control unit outputs first and second clock signals having a clock time difference with minimal power according to the control signal.
Abstract translation: 目的：提供一种用于调整时钟定时的装置和使用其的连续时间Δ-Σ调制器，以通过调整CT（连续时间）积分器和DAC（数字模拟转换器）的时间差来补偿 DAC时钟和量化器时钟。 构成：功率检测单元（110）分别对应于两个或更多个时钟时间差的输入信号的功率进行检测。 从输入信号检测的功率与具有噪声传递特性的能量成比例。 功率检测单元确定输入信号的噪声传递特性。 功率检测单元产生指定检测到的最小功率的时钟时间差的控制信号。 定时控制单元（120）接收参考时钟和控制信号。 定时控制单元根据控制信号输出具有最小功率的时钟时间差的第一和第二时钟信号。
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公开(公告)号：KR101059460B1
公开(公告)日：2011-08-25
申请号：KR1020080097842
申请日：2008-10-06
Applicant: 한국전자통신연구원
CPC classification number: H03M1/162
Abstract: 본 발명은 알고리즘 아날로그-디지털 변환기(Analog-to-Digital Converter : ADC)에 관한 것으로, 본 발명에 따른 알고리즘 ADC는, 전처리 증폭기가 공유되는 구조로 플래시 ADC를 구성함으로써 플래시 ADC에 사용되는 전처리 증폭기의 갯수를 줄여 칩 면적을 감소시킬 수 있는 것을 특징으로 한다. 또한, 요구되는 해상도에 따라 MDAC에 포함된 연산 증폭기의 대역폭을 동적으로 줄여나감으로써 전력 소모를 최소화할 수 있는 것을 특징으로 한다.
알고리즘 ADC, 동적 가변 대역폭 증폭기, 바이어스, 플래시 ADC, MDACAbstract translation: 本发明涉及一种模数转换器（ADC），并且根据本发明的算法ADC包括预处理放大器 通过减少芯片数量可以减小芯片面积。 此外，包含在MDAC中的运算放大器的带宽根据所需的分辨率动态地降低，由此使功耗最小化。
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公开(公告)号：KR1020110073170A
公开(公告)日：2011-06-29
申请号：KR1020100027689
申请日：2010-03-29
Applicant: 한국전자통신연구원
CPC classification number: H03B5/24 , H03B5/1215 , H03B5/1228 , H03B5/1246 , H03B2201/0208
Abstract: PURPOSE: A low voltage LC voltage controlled oscillator(VCO) is provided to overcome the entire phase noise problems by eliminating a current source and minimizing 1/f noises. CONSTITUTION: An LC resonance circuit(310) includes an inductor(L1), and a capacitor(C1). The inductor is in connection with a power terminal(VDD), and the capacitor is in parallel with the inductor. Both end parts of the inductor and the capacitor are in connection with output nodes. An amplifying circuit(320) includes a pair of transistors(M1, M2). The gate nodes of the transistors are in connection with a bias voltage through resistors(R1, R2). A bias voltage supplying circuit(330) includes a transistor(M3) in connection with a source node through a capacitor(C2).
Abstract translation: 目的：提供低压LC压控振荡器（VCO），通过消除电流源和最小化1 / f噪声来克服整个相位噪声问题。 构成：LC谐振电路（310）包括电感器（L1）和电容器（C1）。 电感器与电源端子（VDD）连接，电容器与电感器并联。 电感器和电容器的两端都与输出节点连接。 放大电路（320）包括一对晶体管（M1，M2）。 晶体管的栅极节点与通过电阻（R1，R2）的偏置电压相连。 偏置电压供给电路（330）包括通过电容器（C2）与源极节点连接的晶体管（M3）。
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公开(公告)号：KR1020110067735A
公开(公告)日：2011-06-22
申请号：KR1020090124438
申请日：2009-12-15
Applicant: 한국전자통신연구원
CPC classification number: H03M7/3004 , H03M7/3033 , H03M7/304
Abstract: PURPOSE: A coefficient multiplier with a coefficient averaging technique and digital delta-sigma modulator using the same are provided to form a coefficient multiplier which occupies a small chip size, thereby simplifying the entire structure. CONSTITUTION: A coefficient multiplier(600) comprises a first cascade multiplier(610a), a second cascade multiplier(610b), and a switch(630). The first cascade multiplier has 2^1 coefficient. The second cascade multiplier has 2^2 coefficient. The switch alternatively outputs output signals of the first and second cascade multipliers according to a switch control signal. A digital delta-sigma modulator obtains high resolution information by averaging the output signals by oversampling. An effective output value of the coefficient multiplier is 3 corresponding to the average value of final output signals.
Abstract translation: 目的：提供具有系数平均技术的系数乘法器和使用其的数字Δ-Σ调制器以形成占用小芯片尺寸的系数乘法器，从而简化了整个结构。 构成：系数乘法器（600）包括第一级联乘法器（610a），第二级联乘法器（610b）和开关（630）。 第一级联乘法器具有2 ^ 1系数。 第二级联乘法器具有2 ^ 2系数。 交换机根据开关控制信号交替地输出第一和第二级联乘法器的输出信号。 数字Δ-Σ调制器通过过采样对输出信号进行平均而获得高分辨率信息。 系数乘法器的有效输出值与最终输出信号的平均值相对应。
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