公开(公告)号：EP1699276A2

公开(公告)日：2006-09-06

申请号：EP06009477.8

申请日：2002-04-30

Applicant: Neology, Inc.

Inventor： Martinez de Velasco Cortina, Francisco ,  Riezler, Manfred

IPC: H05K3/06

CPC classification number: G06K19/0723 ,  G06K19/07 ,  G06K19/07718 ,  G06K19/07745 ,  G06K19/07749 ,  G06K19/0775 ,  G06K19/07758 ,  G06K19/0776 ,  G06K19/07771 ,  G06K19/07779 ,  G06K19/07783 ,  G06K2019/0629 ,  H01L2924/0002 ,  H05K1/0269 ,  H05K1/0274 ,  H05K1/0393 ,  H05K3/067 ,  H05K2201/0133 ,  H05K2201/09781 ,  H05K2201/09936 ,  H05K2201/2054 ,  H05K2203/0143 ,  H05K2203/1545 ,  H01L2924/00

Abstract: A method is disclosed of forming a pattern in a metallized region, the method comprising: transferring a metal etching solution to portions of an exposed surface of the metallized region using a printing process; allowing the etching solution to react with the metallized region to selectively demetallize the surface; and washing the selectively demetallized surface.

Abstract translation: 公开了一种在金属化区域中形成图案的方法，该方法包括：使用印刷工艺将金属蚀刻溶液转移到金属化区域的暴露表面的部分; 使蚀刻溶液与金属化区域反应以选择性脱金属表面; 并洗涤选择性脱金属表面。

公开(公告)号：EP1603244A3

公开(公告)日：2006-02-01

申请号：EP05106730.4

申请日：1997-10-20

Applicant: Koninklijke Philips Electronics N.V.

Inventor： Van der Vleuten, Renatus J. ,  Bruekers, Fons ,  Oomen, Werner

IPC: H03M3/02 ,  H03M7/30 ,  G11B20/00 ,  G11B20/10 ,  H03M7/00 ,  H05K1/02 ,  H05K3/38

CPC classification number: G11B20/10 ,  G11B20/00007 ,  G11B20/10037 ,  G11B20/10527 ,  G11B2020/00065 ,  H03M7/3002 ,  H05K1/0266 ,  H05K3/381 ,  H05K2201/09936 ,  H05K2203/161

Abstract: A transmitter is disclosed for transmitting an audio signal. The transmitter comprises an input terminal (1) for receiving the audio signal, a 1-bit A/D converter (4) for A/D converting the audio signal so as to obtain a bitstream signal, a prediction unit (10) for carrying out a prediction step on the bitstream signal so as to obtain a predicted bitstream signal, a signal combination unit (42) for combining the bitstream signal and the predicted bitstream signal so as to obtain a residue bitstream signal, data compression means (154) for data compressing the residual bitstream signal so as to obtain a data compressed residual bitstream signal, and transmission means for applying the data compressed residual bitstream signal to a transmission medium (Figure 1 and 5). Further, a corresponding recording apparatus (Figure 1 and 4) is disclosed.
In addition, another embodiment (Figure 7) for converting the residue bitstream signal into an audio signal is disclosed, as well as a reproducing apparatus (Figure 9) and a receiver apparatus (Figure 10) comprising the other embodiment.

公开(公告)号：EP1377139A1

公开(公告)日：2004-01-02

申请号：EP03011098.5

申请日：2003-05-21

Applicant: ORION ELECTRIC CO., Ltd.

Inventor： Kazuyuki, Nagata

IPC: H05K1/02

CPC classification number: H05K1/0266 ,  H05K1/0295 ,  H05K1/18 ,  H05K2201/09936 ,  H05K2201/09954 ,  H05K2201/10015 ,  H05K2201/10174 ,  H05K2201/10204 ,  H05K2201/10522 ,  H05K2203/168

Abstract: Disclosed is a foolproof polarity indication of poled electronics parts or devices to be given to a printed circuit board to assure that poled electronics parts and/or devices be correctly mounted in respect of their polarities to meet occasional requirements dependent on different specifications. Each pair of terminal holes (1a,1b) are allotted to a given poled electronics part or device. Two symbols (2a,2b) representative of such electronics part or device are arranged side by side on either side of the line drawn from one to the other terminal hole. The poled electronics part or device symbols are of reversed polarities. This dual symbol arrangement is effective to draw workers' attention in mounting electrode components in terms of their polarities. When extra components (S) or dummy ones are combined with such a poled component, they are encircled by a boundary line (6), thereby showing the correct polarity direction of the poled component in respect of whether it is enclosed or not.

Abstract translation: 公开的是必须考虑到印刷电路板，以确保没有极化电子部件和/或装置被正确地安装在相对于它们的极性，以满足依赖于不同规格的偶然要求极化电子部件或装置的万无一失极性指示。 每一对端子孔（1A，1B）被分配给一个给定的极化电子部分或装置。 两个符号（2A，2B）代表寻求电子部分或装置被并排布置在从一个绘制到另一端孔的线的两侧。 极化的电子部件或装置的符号反转极性。 这双符号设置可有效吸引工人的注意力，在它们的极性方面安装电极组件。 当附加组件（S）或虚设那些与寻求极化组分组合，它们由边界线（6）包围，从而示出在关于它是否被封闭或不极化分量的正确的极性方向。

公开(公告)号：EP1189111A4

公开(公告)日：2002-11-06

申请号：EP00919134

申请日：2000-04-18

Applicant: KEM TEC JAPAN CO LTD

Inventor： KARAMATSU HAMATARO

IPC: H05K3/06 ,  G03F1/38 ,  G03F7/20 ,  H05K1/02 ,  H05K3/00 ,  G03F1/08

CPC classification number: G03F7/70541 ,  G03F1/42 ,  G03F7/2014 ,  G03F7/2022 ,  G03F7/70066 ,  G03F7/7035 ,  G03F7/70425 ,  H05K1/0266 ,  H05K3/0002 ,  H05K3/0008 ,  H05K3/0082 ,  H05K2201/09936 ,  H05K2201/09972 ,  H05K2203/056

Abstract: A production device for a printed board, capable of a high-yield stepping exposure of a master photo-mask while an identification marking-dependent stepping exposure is effected, a production method for a printed board, and a printed board produced by the method. A split exposure device (A) for a printed board, which exposes multiple times, during an exposure process for a printed board (2), a master mask (3) having a wiring pattern region (3a) and identification mark regions (3c1) to (3c3) surrounding the region (3a) while its exposure position relative to the printed board (2) is moved sequentially, wherein the master mask (3) is provided on the surface to be exposed of the printed board (2), and an opaque shielding member (4) on the surface opposite to the printed board (2) of the master mask (3) so that the shielding member (4) selectively shields the identification mark regions (3c1) to (3c3) of the master mask (3).

Abstract translation: 目的是提供一种印刷电路板制造装置中，印刷电路板制造方法和印刷电路板由此产生，其中一个原始光掩模的曝光逐步可以通过考虑识别标记被执行以提高产量。 以分步曝光装置“A”用于其中的印刷电路板进行曝光工序（2）基底以原始掩模（3）具有布线图案区域（3a）和识别标记区（3C1）至（3C3）周围的 布线图案区域（3a）的露出阶段性的次多元化到印刷电路板基片（2），而移依次部位露出，原始掩模（3）被布置成面对印刷电路板的基板（2）表面暴露 ; 不透明掩模元件上（4）在印刷电路板的另一侧是其中，布置基板设置在所述原始掩模（3）的一侧上（2）; 和不透明掩模元件（4）选择性掩模识别标记制作区域（3C1）至（3C3）的原始掩模（3）。

公开(公告)号：EP0448702A4

公开(公告)日：1992-07-08

申请号：EP90916555

申请日：1990-10-10

Applicant: THE FOXBORO COMPANY

Inventor： VERNON, ROBERT, D.

IPC: H01L21/60 ,  H01L23/495 ,  H01L23/544 ,  H05K1/02 ,  H05K3/00 ,  H05K3/06 ,  H01R43/00 ,  B32B3/10 ,  G03C5/00 ,  H05K3/02

CPC classification number: H01L24/86 ,  H01L23/49572 ,  H01L23/544 ,  H01L2223/54413 ,  H01L2223/54473 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01038 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/3025 ,  H05K1/0266 ,  H05K3/0082 ,  H05K3/064 ,  H05K2201/09927 ,  H05K2201/09936 ,  H05K2203/0195 ,  H05K2203/0505 ,  H05K2203/0551 ,  H05K2203/107 ,  H05K2203/1545 ,  H01L2924/00

Abstract: An automated method for continuously patterning a tape with a plurality of different interconnection patterns, to which an integrated circuit may be bonded using tape automated bonding, including selectively exposing a portion of a photographic film layer (48) of the tape to computer-directed energy forming an integrated circuit interconnection pattern, and an identifying pattern, and developing the film (48) to provide an image of the interconnection pattern. A photoprocessable layer of the tape is then exposed through the film layer (48) to directed energy and processed in conjunction with a conductive layer (44) in order to provide conductors which correspond to the interconnection pattern being fabricated. Also disclosed is a method of high speed patterning of a tape. Further disclosed is a novel material and apparatus for generating TAB tape.

公开(公告)号：EP0251191A2

公开(公告)日：1988-01-07

申请号：EP87109096.5

申请日：1987-06-24

Applicant: E.I. DU PONT DE NEMOURS AND COMPANY

Inventor： Taylor, Harvey Walter, Jr.

IPC: H05K3/34 ,  H05K3/22 ,  G03F7/26

CPC classification number: G03F7/34 ,  H05K1/0266 ,  H05K3/0079 ,  H05K3/28 ,  H05K2201/09936 ,  H05K2203/0514 ,  H05K2203/0537 ,  H05K2203/122 ,  H05K2203/161

Abstract: Nomenclature is applied to a soldermask surface employing a peel apart film prior to application of molten solder.

Abstract translation: 在施加熔融焊料之前，使用剥离膜将命名法应用于焊接表面。

公开(公告)号：US20230262882A1

公开(公告)日：2023-08-17

申请号：US17651436

申请日：2022-02-17

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Hiroyuki Mori

IPC: H05K1/02 ,  G01B21/24

CPC classification number: H05K1/0269 ,  G01B21/24 ,  H05K2201/09936

Abstract: Embodiments of present invention provide a multilayer printed circuit board. The printed circuit board includes a first conducting layer (CL) having a first measurement mark area (MMA) and a second CL having a second MMA. A first polygonal measurement mark (MM) in the first MMA and a second and a third polygonal MM in the second MMA, wherein the second polygonal MM is positioned along an extended first angle bisector bisecting a first vertex of the first polygonal MM and a first vertex of the second polygonal MM is substantially aligned with the first vertex of the first polygonal MM, and wherein the third polygonal MM is positioned along an extended second angle bisector bisecting a second vertex of the first polygonal MM and a first vertex of the third polygonal MM is substantially aligned with the second vertex of the first polygonal MM.

公开(公告)号：US20180255649A1

公开(公告)日：2018-09-06

申请号：US15760487

申请日：2016-09-16

Applicant: AT&S (China) Co. Ltd.

Inventor： Annie Tay ,  Nikolaus Bauer-Oeppinger ,  Giordano DiGregorio ,  Philips DAI

IPC: H05K3/46 ,  H05K3/00 ,  H05K3/32 ,  H05K3/40 ,  H05K3/10 ,  H05K3/02

CPC classification number: H05K3/4682 ,  H05K1/0269 ,  H05K1/0271 ,  H05K3/0097 ,  H05K3/022 ,  H05K3/108 ,  H05K3/32 ,  H05K3/4007 ,  H05K3/4638 ,  H05K2201/068 ,  H05K2201/09918 ,  H05K2201/09936 ,  H05K2203/0156 ,  H05K2203/0264 ,  H05K2203/1536

Abstract: A semifinished product with a sacrificial structure and two component carriers releasably formed on opposing main surfaces of the sacrificial structure. The sacrificial structure includes a central structure and releasing layers on or over both opposing main surfaces of the central structure The central structure includes a dummy core being covered, in particular fully, on or over both main surfaces thereof with a respective one of two spatially separated sections of separate material, in particular separate dielectric material.

公开(公告)号：US20170140616A1

公开(公告)日：2017-05-18

申请号：US14940708

申请日：2015-11-13

Applicant: AVEXIR TECHNOLOGIES CORPORATION

Inventor： Han-Hung CHENG ,  Chi-Fen KUO

IPC: G08B5/36 ,  G11C11/401

CPC classification number: G08B5/36 ,  G11C5/00 ,  G11C5/04 ,  H01L23/00 ,  H01L25/167 ,  H01L27/00 ,  H05K1/0269 ,  H05K3/288 ,  H05K2201/0989 ,  H05K2201/09936

Abstract: A dynamic random access memory includes a main body which has a substrate portion and a light-emitting portion and a transmission port, the substrate portion includes a board and a first coating layer, the board has a light-transmittable portion and a first face, the first coating layer is coated on the first face and has an emergent light-transmittable portion corresponding to the light-transmittable portion, and the substrate portion has a memory module. The transmission port is disposed on the substrate portion and electrically connected with the memory module. The electronic device includes the dynamic random access memory and further includes a shell portion. The shell portion is covered on two opposite lateral faces of the dynamic random access memory and at least shields the light-emitting portion, and the shell portion further has a second light-transmittable portion corresponding to the emergent light-transmittable portion.

公开(公告)号：US09585243B1

公开(公告)日：2017-02-28

申请号：US14757470

申请日：2015-12-23

Applicant: OCZ Storage Solutions, Inc.

Inventor： Stephen K. Pardoe ,  Nigel Rowe

IPC: B32B3/02 ,  H05K1/02 ,  H05K3/00

CPC classification number: H05K1/0266 ,  H05K1/0269 ,  H05K3/0047 ,  H05K3/0052 ,  H05K2201/09063 ,  H05K2201/09145 ,  H05K2201/09936 ,  H05K2203/0228

Abstract: Methods of manufacturing circuit boards and circuit boards formed thereby to have a surface that is configured to receive circuitry and a notch of a selectable configuration in a lateral edge along the surface of the circuit board boards, and where the selectable configuration is configured to convey identifying information relating to the circuit boards. Such a circuit board can be produced from a panel containing one or more circuit boards, wherein at least one circuit board has a border adjoined and defined by a partition feature that is configured to enable the circuit board to be physically separated from other portions of the panel. Notches having the same of varying selectable configurations may be formed on the at least one circuit board during the manufacturing of the circuit board.

Abstract translation: 制造电路板和电路板的方法由此形成，所述电路板和电路板具有被配置成在沿着电路板板的表面的横向边缘中接收电路和可选择配置的凹口的表面，并且其中可选配置被配置为传送识别 有关电路板的信息。 这样的电路板可以由包含一个或多个电路板的面板制成，其中至少一个电路板具有由划分特征邻接并限定的边界，该分隔特征被配置为使得电路板能够与 面板。 在制造电路板期间，可以在至少一个电路板上形成具有不同可选配置的相同的凹口。