公开(公告)号：US5902438A

公开(公告)日：1999-05-11

申请号：US910280

申请日：1997-08-13

Applicant: Richard Arthur ,  Lyn Holt ,  David Baghurst ,  Gary Lee Nicholls

Inventor： Richard Arthur ,  Lyn Holt ,  David Baghurst ,  Gary Lee Nicholls

IPC: H01R43/00 ,  H05K3/32 ,  H05K3/34 ,  H05K3/40 ,  B32B31/18 ,  H01B1/20 ,  H01R1/00

CPC classification number: H05K3/4069 ,  H05K3/321 ,  H01R43/007 ,  H05K2201/09572 ,  H05K2201/09945 ,  H05K2201/10378 ,  H05K2203/0126 ,  H05K2203/0191 ,  H05K2203/0278 ,  H05K2203/1572 ,  H05K3/3436 ,  H05K3/3484 ,  Y10T156/1057

Abstract: A process for the preparation of an anisotropic conducting material including the steps of providing a strip or sheet of a non-conducting matrix and laminating at least one layer of a release material to each side thereof to form a composite matrix, forming an array of holes in a predetermined pattern in the composite matrix, passing the matrix through a coating head which simultaneously fills the holes in the array in the composite matrix from both sides of the matrix with a conducting material, curing or drying the composite filled matrix and removing at least one layer of release material from each side of the matrix.

Abstract translation: 一种用于制备各向异性导电材料的方法，包括以下步骤：提供非导电基质的条或片，并将至少一层释放材料层压到其每一侧以形成复合基质，形成孔阵列 在复合基质中以预定的图案，使基质通过涂层头，涂层头同时用导电材料从基体的两侧填充复合基体中的阵列中的孔，固化或干燥复合填充的基质并至少除去 从矩阵的每一侧的一层释放材料。

公开(公告)号：US5856636A

公开(公告)日：1999-01-05

申请号：US810356

申请日：1997-03-03

Applicant: David W. Sanso

Inventor： David W. Sanso

IPC: H05K1/00 ,  H05K1/02 ,  H05K1/11 ,  H05K3/42 ,  H05K1/03

CPC classification number: H05K1/116 ,  H05K1/0266 ,  H05K1/0287 ,  H05K1/0298 ,  H05K2201/0133 ,  H05K2201/09381 ,  H05K2201/09781 ,  H05K2201/09945 ,  H05K2201/10303 ,  H05K2203/1189 ,  H05K3/429 ,  Y10T29/49126

Abstract: Electronic circuit prototype wiring board is fabricated with layers of electrically conductive material separated by layers of dielectric material. Contact pads of electrically conductive material are arrayed on a surface of the board. Columns of electrically conductive material extend upward from each of the conductive layers to selected contact pads, passing through perforations in any intermediate layers above, such that each of the pads is in electrical communication with only one of the conductive layers. All of the pads connected to a common conductive layer are of a similar geometric plan form which is associated with that layer and which is different and distinguishable from the plan form of pads in electrical communication with any other of the conductive layers. In an alternative embodiment, the wiring board is fabricated of an elastic dielectric material. Access points for each conductive layer of the board are identified by similar geometric shapes associated with that layer and which are different and distinguishable from shapes identifying access points for any other of the conductive layers. Pins fabricated of electrically conductive material are inserted into the elastic dielectric material to establish electrical contact with a desired conductive layer and be retained by the dielectric material to serve as a wiring post.

Abstract translation: 电子电路原型布线板由电介质材料层隔开的导电材料层制成。 导电材料的接触垫排列在板的表面上。 导电材料的列从每个导电层向上延伸到选定的接触焊盘，穿过上面任何中间层的穿孔，使得每个焊盘仅与一个导电层电连通。 连接到公共导电层的所有焊盘具有类似的几何平面形式，其与该层相关联，并且与与任何其它导电层电连通的焊盘的平面形式不同且可区分。 在替代实施例中，布线板由弹性介电材料制成。 板的每个导电层的接入点由与该层相关联的类似几何形状标识，并且与形成的任何其他导电层的识别不同的形状区分开来。 由导电材料制成的引脚插入到弹性电介质材料中以与期望的导电层建立电接触并被电介质材料保持以用作布线柱。

公开(公告)号：US5509815A

公开(公告)日：1996-04-23

申请号：US255687

申请日：1994-06-08

Applicant: Sungho Jin ,  Mark T. McCormack

Inventor： Sungho Jin ,  Mark T. McCormack

IPC: B23K35/02 ,  B23K35/14 ,  H05K3/34 ,  H05K3/36 ,  H01R9/09

CPC classification number: B23K35/0222 ,  H05K3/3436 ,  B23K35/0227 ,  B23K35/0244 ,  H01L2924/0002 ,  H05K2201/0215 ,  H05K2201/083 ,  H05K2201/09945 ,  H05K2201/10378 ,  H05K2201/10424 ,  H05K2203/0235 ,  H05K2203/0769 ,  H05K2203/104 ,  Y02P70/613

Abstract: Electronic devices having at least two components wire mating contact pads are provided with high-aspect-ratio solder joints between the mating pads. These joints ar formed by placing a composite solder medium containing solder wires in an electrically insulating matrix such that at least two solder wires are in contact with the mating pads, and fusing the wires to the pads. The insulating matrix with remainder of solder wires is then optionally removed from between the said at least two component. The composite solder medium is formed by preparing an elongated body of solder wires in an insulating matrix and cutting off slices of the composite solder medium, the solder wires having a high-aspect-ratio of length to the diameter. Alternatively sheets of the composite solder medium are prepared by magnetically aligning solder coated magnetic particles into columns arranged transverse of an insulating matrix and heating sufficiently to fuse the solder in each column into a continuously conducting solder path.

Abstract translation: 具有至少两个部件的电子设备配线接触焊盘在配合焊盘之间设置有高纵横比焊接点。 这些接头通过将包含焊丝的复合焊料介质放置在电绝缘基体中而形成，使得至少两个焊丝与配合焊盘接触，并将焊丝熔合到焊盘。 然后可选地从所述至少两个部件之间移除具有剩余焊丝的绝缘基体。 复合焊料介质通过在绝缘基体中制备细长的焊丝体并且切断复合焊料介质的切片而形成，该焊丝具有与直径的长宽比的高纵横比。 或者，复合焊料介质的片材通过将焊接涂覆的磁性颗粒磁化地排列成横向于绝缘矩阵布置的列并充分加热以将每个列中的焊料熔合成连续导电的焊接路径来制备。

公开(公告)号：US5366140A

公开(公告)日：1994-11-22

申请号：US129668

申请日：1993-09-30

Applicant: David C. Koskenmaki ,  Clyde D. Calhoun

Inventor： David C. Koskenmaki ,  Clyde D. Calhoun

IPC: B23K35/02 ,  H01L21/52 ,  H01L21/60 ,  H01L23/498 ,  H05K3/10 ,  H05K3/32 ,  B23K35/00 ,  B23K35/14

CPC classification number: H01L24/83 ,  B23K35/0222 ,  H01L23/49883 ,  H01L24/29 ,  H05K3/323 ,  H01L2224/29298 ,  H01L2224/8319 ,  H01L2224/838 ,  H01L2924/00011 ,  H01L2924/00013 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01023 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01061 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01327 ,  H01L2924/0781 ,  H01L2924/09701 ,  H01L2924/12033 ,  H01L2924/14 ,  H05K2201/09945 ,  H05K2201/10378 ,  H05K2201/10719 ,  H05K2203/0338 ,  H05K2203/0425 ,  H05K2203/128 ,  H05K3/102 ,  Y10T428/12 ,  Y10T428/12014

Abstract: The present invention provides a method for providing an array of metal microbeads on a substrate, preferably in a regular pattern of very fine, uniform size microspheres or microbeads at precise spacing or scale previously unachievable. The method of the present invention comprises the steps of providing a metal layer on a substrate that is partitioned into metal regions; heating the metal layer to a temperature sufficient to melt the metal and to permit beading of the layer into discrete microbeads.

Abstract translation: 本发明提供了一种用于在衬底上提供金属微珠阵列的方法，优选地以非常精细，均匀尺寸的微球或微珠的规则图案以精确的间隔或尺度提前预先不可实现。 本发明的方法包括在分隔成金属区域的基板上设置金属层的步骤; 将金属层加热到足以熔化金属的温度，并允许该层将珠粒串联成离散的微珠。

公开(公告)号：US5282312A

公开(公告)日：1994-02-01

申请号：US816634

申请日：1991-12-31

Applicant: Thomas H. DiStefano ,  Igor Y. Khandros ,  Gary W. Grube

Inventor： Thomas H. DiStefano ,  Igor Y. Khandros ,  Gary W. Grube

IPC: H01L21/48 ,  H01L23/538 ,  H05K1/00 ,  H05K3/40 ,  H05K3/42 ,  H05K3/46 ,  H05K3/36

CPC classification number: H05K3/462 ,  H01L21/4857 ,  H01L23/5383 ,  H01L23/5385 ,  H01R12/523 ,  H05K1/0287 ,  H05K1/029 ,  H01L2924/0002 ,  H01L2924/09701 ,  H05K1/0298 ,  H05K2201/0195 ,  H05K2201/0305 ,  H05K2201/09509 ,  H05K2201/09536 ,  H05K2201/096 ,  H05K2201/09609 ,  H05K2201/09945 ,  H05K2201/10378 ,  H05K2201/10666 ,  H05K2203/175 ,  H05K3/4038 ,  H05K3/4069 ,  H05K3/4602 ,  H05K3/4623 ,  Y10T29/49126 ,  Y10T29/49155 ,  Y10T29/49165

Abstract: Multilayer circuit assemblies are made by stacking circuit panels having contacts on their top surfaces, through conductors extending between top and bottom surfaces and terminals connected to the bottomend of each through conductor. The terminals and contacts are arranged so that when the panels are stacked the terminals on the bottom of one panel are in alignment with the contacts on the top surface of the immediately underlying panel. The panels are selectively treated on their top and/or bottom surfaces so as to selectively disconnect or connect each contact to a terminal on the bottom surface of the same panel. For example, the top surface of the panel may be selectively etched to disconnect a contact from one through conductor and hence from the associated terminal. The aligned terminals and contacts are nonselectively connected to one another at each interface so that wherever a terminal and contact on adjacent panels are aligned with one another there are connected to one another. This forms composite vertical conductors extending through a plurality of the panels. The selective treatment of the panel top and bottom surfaces provides selective interruptions in the vertical conductors. A circuit panel precursor having the through conductors and methods of making the same are also provided.

Abstract translation: 多层电路组件通过在其顶表面上堆叠具有触点的电路板，通过在顶表面和底表面之间延伸的导体以及连接到每个贯通导体的底端的端子而形成。 端子和触点被布置成使得当面板堆叠时，一个面板的底部上的端子与紧邻的底板的顶表面上的触点对准。 在其顶表面和/或底表面上选择性地处理这些面板，以便选择性地将每个接触件断开或连接到同一面板的底表面上的端子。 例如，可以选择性地蚀刻面板的顶表面以将接触从一个导体断开，并因此从相关联的端子断开。 对准的端子和触点在每个接口处彼此非选择性地连接，使得相邻面板上的端子和触点彼此对准的位置彼此连接。 这形成延伸穿过多个面板的复合垂直导体。 面板顶部和底部表面的选择性处理在垂直导体中提供选择性的中断。 还提供了具有贯通导体的电路板前体及其制造方法。

公开(公告)号：US5240761A

公开(公告)日：1993-08-31

申请号：US237546

申请日：1988-08-29

Applicant: Clyde D. Calhoun ,  Maurice J. Fleming

Inventor： Clyde D. Calhoun ,  Maurice J. Fleming

IPC: C09J7/00 ,  C09J7/02 ,  H05K3/32

CPC classification number: C09J7/00 ,  C09J7/0203 ,  C09J7/0207 ,  H05K3/323 ,  C09J2201/32 ,  C09J2201/602 ,  H05K2201/0221 ,  H05K2201/023 ,  H05K2201/09945 ,  Y10T428/24413 ,  Y10T428/24545 ,  Y10T428/256 ,  Y10T428/258 ,  Y10T428/28 ,  Y10T428/2852 ,  Y10T428/287 ,  Y10T428/2891

Abstract: Electrically conductive elements on two substrates can be electrically interconnected by an adhesive tape containing electrically conductive particles, most of which are substantially uniformly spaced from their six nearest neighbors. Preferably the particles are spherical and of substantially equal diameter slightly exceeding the thickness of the adhesive layer. The adhesive tape can be made by forming a dense monolayer of the particles, covering a stretchable adhesive layer with that dense monolayer, biaxially stretching the adhesive layer to separate each particle from other particles of the monolayer, and then embedding the particles either into that adhesive layer or into the adhesive layer of another tape.

Abstract translation: 两个基板上的导电元件可以通过含有导电颗粒的粘合带电互连，其中大部分与其六个最近的邻近部分基本均匀地间隔开。 优选地，颗粒是球形的并且具有基本相等的直径略微超过粘合剂层的厚度。 胶带可以通过形成致密的单层颗粒，用该致密单层覆盖可拉伸的粘合剂层，双轴拉伸粘合剂层以将每个颗粒与单层的其它颗粒分离，然后将颗粒包埋在该粘合剂中 层或另一条胶带的粘合剂层。

公开(公告)号：US5041183A

公开(公告)日：1991-08-20

申请号：US462040

申请日：1990-01-09

Applicant: Akio Nakamura ,  Osami Hayashi ,  Hideki Tabei

Inventor： Akio Nakamura ,  Osami Hayashi ,  Hideki Tabei

IPC: H01R11/01 ,  H01R4/04 ,  H01R13/24 ,  H05K1/18 ,  H05K3/30 ,  H05K3/32 ,  H05K3/36

CPC classification number: H05K3/323 ,  H01R4/04 ,  H01R12/714 ,  H01R13/2414 ,  H05K1/181 ,  H05K2201/0129 ,  H05K2201/09945 ,  H05K2201/10378 ,  H05K2201/10977 ,  H05K2203/1189 ,  H05K3/305 ,  H05K3/321 ,  H05K3/361 ,  Y10T156/1075 ,  Y10T29/4922

Abstract: The inventive interconnector, which is used for electrically connecting two arrays of electrodes on two circuit boards, etc., is a striped sheet composed of alternately arranged strips of an insulating adhesive hot-melt resin and strips of a conductive adhesive hot-melt resin composition. The interconnector is prepared by stacking a film of the insulating resin coated on one surface with the conductive composition, integrating the stack into an integral block and slicing the block in a plane perpendicular to the surface of the stacked films. Alternatively, the interconnector is composed of a matrix of an insulating adhesive hot-melt resin and regularly distributed spots of a conductive adhesive hot-melt resin composition. Such an interconnector can be prepared by stacking alternately numbers of the above mentioned striped sheets and sheets of the insulating adhesive hot-melt resin one on the other, integrating the stack into an integral block and slicing the block in a plane perpendicular to the running direction of the conductive strips in the conductive sheets.

Abstract translation: 用于电连接两个电路板上的两个电极阵列的本发明的互连器是由交替布置的绝缘粘合剂热熔树脂条和导电粘合剂热熔树脂组合物条 。 通过将涂覆在一个表面上的绝缘树脂的膜与导电组合物层叠，将叠层整合成整体块并在垂直于堆叠膜的表面的平面中切割块来制备互连器。 或者，互连器由绝缘粘合剂热熔树脂的基体和导电粘合剂热熔树脂组合物的规则分布的点组成。 这样的互连器可以通过将上述条形片材和绝缘粘合剂热熔树脂片材交替堆叠而制成，将堆叠整合成整体块，并在与行进方向垂直的平面中切片块 的导电片中的导电条。

公开(公告)号：US4931598A

公开(公告)日：1990-06-05

申请号：US292050

申请日：1988-12-30

Applicant: Clyde D. Calhoun ,  David C. Koskenmaki

Inventor： Clyde D. Calhoun ,  David C. Koskenmaki

IPC: H01R4/04 ,  H05K3/32

CPC classification number: H01R4/04 ,  H05K3/323 ,  H05K2201/09945 ,  H05K2201/10234 ,  H05K2203/0338

Abstract: The invention provides a sheet material adapted to make bonded electrical connection to an array of closely spaced conductive terminal pads. The material may be provided as a roll of an elongated flexible connector tape. The sheet material of the invention comprises a thin, flexible insulating substrate and a plurality of longitudinally-extending, regularly-spaced, metal conductive members. The sheet may also include an adhesive layer that may cover the conductive members or at least a portion of the conductive members may extend above the adhesive layer. The conductive members may be supported and held on the substrate or may be suspended in the adhesive, out of contact with the substrate.

Abstract translation: 本发明提供了一种片材，其适于使得与紧密间隔的导电端子焊盘的阵列的结合电连接。 材料可以被设置为细长柔性连接器带的卷。 本发明的片材包括薄的柔性绝缘基底和多个纵向延伸的规则间隔的金属导电构件。 片材还可以包括可以覆盖导电构件的粘合剂层，或者导电构件的至少一部分可以在粘合剂层的上方延伸。 导电构件可以被支撑并保持在基底上，或者可以悬挂在粘合剂中，与基底不接触。

公开(公告)号：US4361634A

公开(公告)日：1982-11-30

申请号：US7731

申请日：1979-01-30

Applicant: Robert Miller

Inventor： Robert Miller

IPC: H05K1/00 ,  H05K3/00 ,  H05K3/46 ,  G03F5/00

CPC classification number: H05K3/0002 ,  H05K1/0287 ,  H05K1/0289 ,  H05K1/0298 ,  H05K2201/09945 ,  H05K2203/056 ,  H05K3/4641 ,  Y10S428/901 ,  Y10S430/152

Abstract: A multilayer printed circuit board structure and a method for generating artwork masters for the manufacture thereof. The multilayer board comprises universal internal layers of predefined circuit patterns. The internal layers include power and ground planes, and for boards having high component and circuit density, one or two signal crossover layers with short, equal-length runs oriented transversely to the runs of an adjacent outermost signal layer. Electrical interconnections between layers of the circuit board are effected by interlayer conductors such as pins or plated-through holes at predefined locations. The artwork masters for the outermost layers are generated utilizing two degrees of layout precision. A universal layout master having interconnection pads and parallel circuit runs extending across the entire surface of the board is first prepared using a high degree of precision. The universal layout master is then superposed with other layout masters including a component matrix and utilized to generate a composite artwork master having relatively short circuit runs of a second degree of precision interconnecting the parallel runs and the pads. A tool for a unique outermost layer is then reproduced from the composite artwork master utilizing an artwork master of another layer to control interlayer registration.

Abstract translation: 一种多层印刷电路板结构和用于制造艺术品主人的方法。 多层板包括预定电路图案的通用内层。 内层包括电源和接地层，对于具有高分量和电路密度的板，一个或两个信号交叉层具有横向于邻近的最外层信号层的运行的短等长的运行。 电路板层之间的电气互连通过层间导体（例如在预定位置处的引脚或电镀通孔）来实现。 使用两种布局精度生成最外层的艺术品主。 首先，使用高精度地准备具有互连焊盘和延伸穿过板的整个表面的并行电路运行的通用布局主机。 然后，通用布局主体与包括组件矩阵的其他布局主体叠加，并且用于生成具有互连平行和焊盘的第二精度的相对短路运行的复合图稿母版。 然后，使用另一层的艺术作品主体，从复合艺术品母版再现用于唯一最外层的工具，以控制层间配准。

公开(公告)号：TW330338B

公开(公告)日：1998-04-21

申请号：TW083111014

申请日：1994-11-26

Applicant: 孟尼蘇泰礦務及製造公司

Inventor： 大維.克拉倫斯.克斯肯馬奇 ,  克萊德.大維.卡豪恩

IPC: H01L

CPC classification number: H01R13/2414 ,  H01R4/04 ,  H05K3/323 ,  H05K2201/083 ,  H05K2201/09945 ,  H05K2203/0113 ,  H05K2203/0338 ,  H05K2203/104 ,  Y10T428/1452 ,  Y10T428/25 ,  Y10T428/28

Abstract: 本發明係提供導電性薄片材料(10)，其含有導電性粒子柱狀物，該粒子係排成一線而在該導電性薄片材料(10)之側面間形成連續柱狀物(19)。此等粒子柱狀物(19)係經安排，以使該薄片經其厚度方向為導電性，且在側面方向為電絕緣性。本發明亦提供製造此種導電性薄片材料(10)之方法。本發明能夠在極微細間距下，以一種精密而有規則排列，提供導電性通路。

Abstract in simplified Chinese: 本发明系提供导电性薄片材料(10)，其含有导电性粒子柱状物，该粒子系排成一线而在该导电性薄片材料(10)之侧面间形成连续柱状物(19)。此等粒子柱状物(19)系经安排，以使该薄片经其厚度方向为导电性，且在侧面方向为电绝缘性。本发明亦提供制造此种导电性薄片材料(10)之方法。本发明能够在极微细间距下，以一种精密而有守则排列，提供导电性通路。