公开(公告)号：KR1020160061342A

公开(公告)日：2016-05-31

申请号：KR1020167007707

申请日：2013-09-27

Applicant: 르네사스 일렉트로닉스 가부시키가이샤

Inventor： 시모떼,요시까즈 ,  바바,신지 ,  이와사끼,도시히로 ,  나까가와,가즈유끼

IPC: H01L23/498 ,  H01L23/50 ,  H01L23/00 ,  H01L21/56 ,  H01L21/683

CPC classification number: H01L24/17 ,  H01L21/561 ,  H01L21/563 ,  H01L21/6836 ,  H01L21/78 ,  H01L23/3128 ,  H01L23/3142 ,  H01L23/49805 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/49894 ,  H01L23/50 ,  H01L23/562 ,  H01L23/564 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/32 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/81 ,  H01L24/97 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2224/0401 ,  H01L2224/05009 ,  H01L2224/05022 ,  H01L2224/05124 ,  H01L2224/05572 ,  H01L2224/11 ,  H01L2224/1134 ,  H01L2224/1146 ,  H01L2224/1147 ,  H01L2224/11849 ,  H01L2224/13012 ,  H01L2224/13014 ,  H01L2224/13016 ,  H01L2224/13076 ,  H01L2224/13082 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13116 ,  H01L2224/13139 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/16055 ,  H01L2224/16105 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16237 ,  H01L2224/1713 ,  H01L2224/32225 ,  H01L2224/45015 ,  H01L2224/48091 ,  H01L2224/48106 ,  H01L2224/48227 ,  H01L2224/48235 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2224/81 ,  H01L2224/81191 ,  H01L2224/81385 ,  H01L2224/814 ,  H01L2224/81815 ,  H01L2224/83 ,  H01L2224/83104 ,  H01L2224/85 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2924/014 ,  H01L2924/05442 ,  H01L2924/0665 ,  H01L2924/10253 ,  H01L2924/15311 ,  H01L2924/15321 ,  H01L2924/181 ,  H01L2924/186 ,  H01L2924/2064 ,  H01L2924/351 ,  H05K3/284 ,  H05K3/3436 ,  H05K2201/068 ,  H05K2201/09427 ,  H05K2201/10704 ,  H05K2201/10977 ,  H05K2203/0465 ,  H01L2924/00012 ,  H01L2924/01047 ,  H01L2224/45099 ,  H01L2924/207

Abstract: 일실시형태에의한반도체장치(SP1)는배선기판(2)의기재층(2CR)과반도체칩(3)의사이에, 기재층과밀착되는솔더레지스트막(SR1: 제1 절연층), 솔더레지스트막및 반도체칩과밀착되는수지체(4: 제2 절연층)가적층되어있다. 또한, 솔더레지스트막의선팽창계수는기재층의선팽창계수이상이며, 솔더레지스트막의선팽창계수는수지체의선팽창계수이하이며, 또한기재층의선팽창계수는수지체의선팽창계수보다도작은것이다. 상기구성에의해, 온도사이클부하에기인하는반도체장치의손상을억제하여, 신뢰성을향상시킬수 있다.

Abstract translation: 在根据实施例的半导体器件（SP1）中，与基材层接触的阻焊膜（第一绝缘层SR1）和与该基材层接触的树脂体（第二绝缘层4） 阻焊膜和半导体芯片层叠在布线基板2的基材层（2CR）和半导体芯片（3）之间。 此外，阻焊膜的线膨胀系数等于或大于基材层的线膨胀系数，阻焊膜的线膨胀系数等于或小于 树脂体。 此外，基材层的线膨胀系数小于树脂体的线膨胀系数。 根据上述结构，可以抑制由温度循环负载引起的半导体器件的损坏，从而可以提高可靠性。

公开(公告)号：KR1020140040837A

公开(公告)日：2014-04-03

申请号：KR1020147002253

申请日：2012-04-11

Applicant: 애플 인크.

Inventor： 데그너,브렛더블유. ,  타이스,그레고리

IPC: H01L23/40 ,  H01L23/473 ,  H05K7/12 ,  H05K7/20

CPC classification number: G06F1/20 ,  H01L23/4006 ,  H01L23/427 ,  H01L23/473 ,  H01L2924/0002 ,  H05K3/301 ,  H05K7/12 ,  H05K7/20 ,  H05K7/20254 ,  H05K2201/064 ,  H05K2201/10265 ,  H05K2201/10325 ,  H05K2201/10393 ,  H05K2201/10704 ,  H05K2203/0278 ,  Y10T29/49124 ,  Y10T29/49826 ,  Y10T29/53113 ,  H01L2924/00

Abstract: 인쇄 회로 기판(214)에 실장된 집적 회로(208)를 고정하고 이 집적 회로에 의해 생성되는 초과 열을 제거하며, 컴팩트한 컴퓨팅 환경에서 동작하기에 적합한 낮은 Z 프로파일 통합 열 모듈이 개시된다. 이 통합 열 모듈은, 감소된 풋프린트를 가지며, 집적 회로와 열 접촉하여 인쇄 회로 기판의 제1 표면 상에 배치된 열 제거 어셈블리(202, 204, 206)를 포함한다. 유지 메커니즘(210)은 인쇄 회로 기판의 제2 표면 상에 배치되고, 배커 플레이트(218)는 유지 메커니즘과 인쇄 회로 기판 사이에 배치된다. 적어도 하나의 파스너(212)는 열 제거 어셈블리를 배커 플레이트 및 유지 메커니즘에 고정시키고, 유지 메커니즘은 실질적으로 균일한 유지력이 배커 플레이트에 걸쳐 가해지도록 하고, 그에 의해 집적 회로에 가해지는 토크의 양을 최소화한다.

公开(公告)号：KR1020010041853A

公开(公告)日：2001-05-25

申请号：KR1020007010144

申请日：1999-03-10

Applicant: 메달리언 테크놀로지, 엘엘씨

Inventor： 가르시아,스티브

IPC: H05K3/32

CPC classification number: H01L23/49811 ,  H01L24/29 ,  H01L24/45 ,  H01L24/49 ,  H01L24/83 ,  H01L2224/1134 ,  H01L2224/13144 ,  H01L2224/16 ,  H01L2224/29101 ,  H01L2224/2919 ,  H01L2224/45144 ,  H01L2224/4943 ,  H01L2224/8319 ,  H01L2224/838 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/0102 ,  H01L2924/01023 ,  H01L2924/01033 ,  H01L2924/01039 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/0665 ,  H01L2924/0781 ,  H01L2924/14 ,  H05K3/321 ,  H05K2201/10704 ,  H01L2224/13099 ,  H01L2924/00 ,  H01L2224/45015 ,  H01L2924/207

Abstract: 본발명은전기적기계적으로상호연결한는전자회로조립체들또는전자모듈을제공하는방법및 장치에관한것이다. 집적회로(300)는표면(305)로부터확장되는복수의리드선(302), 착석부분(403)을갖는각각의리드선(302), 및스템부분(402)을포함한다. 인쇄회로기판(400)은집적회로(300)로부터확장된복수의리드선(302)에대응하는복수의도금된관통구(401)를포함한다. 본발명에따른방법은인쇄회로기판(400)의하부표면(404)을집적회로(300)의리드선(302)의착석부분(403)에위치시키는단계와, 각각리드선의스템부분(302)이인쇄회로기판(400)의대응하는도금된관통구(401)안에위치되도록인쇄회로기판(400)을위치결정하는단계를포함한다. 도전성에폭시접착제(602)는그때리드선(302)을가지는구멍(401) 안으로투여되고, 인쇄회로기판(400)과집적회로(300) 사이에단단한전기적및 기계적연결을형성하도록경화된다.

公开(公告)号：KR1020000071795A

公开(公告)日：2000-11-25

申请号：KR1020000021592

申请日：2000-04-24

Applicant: 닛폰 덴키 가부시끼 가이샤

Inventor： 사쿠라이준야

IPC: H05K3/32

CPC classification number: H05K1/112 ,  H01L23/13 ,  H01L23/49816 ,  H01L23/5385 ,  H01L24/06 ,  H01L24/14 ,  H01L24/17 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/0603 ,  H01L2224/13023 ,  H01L2224/1403 ,  H01L2224/14135 ,  H01L2224/16111 ,  H01L2224/16113 ,  H01L2224/16237 ,  H01L2224/16238 ,  H01L2224/17104 ,  H01L2224/8114 ,  H01L2224/81385 ,  H01L2924/00014 ,  H01L2924/12042 ,  H01L2924/3011 ,  H05K1/0298 ,  H05K3/3436 ,  H05K2201/094 ,  H05K2201/09472 ,  H05K2201/10318 ,  H05K2201/10704 ,  H05K2201/10734 ,  H05K2203/041 ,  H05K2203/0415 ,  H05K2203/0465 ,  Y02P70/613 ,  H01L2924/00 ,  H01L2224/05599

Abstract: 본발명은스루홀(through-hole) 또는블라인드비어홀(blind via hole)을필요로하지않는인쇄회로기판으로의접속구조를제공한다. 다층구조의인쇄회로기판은내부층에배선과함께매립되는복수의패드를갖는다. 상기패드상의절연재는패드를노출시키는리세스를형성하기위해인쇄회로기판으로부터제거된다. 반도체패키지는인쇄회로기판상에위치되고, 상기반도체패키지의솔더볼은상기리세스를통해패드에직접접속된다.

公开(公告)号：KR100268460B1

公开(公告)日：2000-10-16

申请号：KR1019960062852

申请日：1996-12-07

Applicant: 삼성전자주식회사

Inventor： 김지상

IPC: H05K13/04

CPC classification number: H05K3/303 ,  H01L24/75 ,  H01L2224/16 ,  H01L2924/14 ,  H05K3/3436 ,  H05K2201/10568 ,  H05K2201/10704 ,  H05K2201/10734 ,  H05K2203/167 ,  Y02P70/613 ,  H01L2924/00

Abstract: PURPOSE: An apparatus for determining position of surface mounting semiconductor IC is provided to enable a surface mounting semiconductor IC to be exactly positioned on a circuit board. CONSTITUTION: A body includes an IC chip, an electric wiring, a substrate, and a wire bonder. A lead pin is protruded on a surface of a surface mounting semiconductor IC to electrically connect to a circuit board. The semiconductor IC is quadrangular shaped and has positioning members(50) on four edge portions thereof to guide a position to be mounted when the semiconductor IC is mounted on the circuit board through a surface mounter. The positioning members(50) are formed at a position higher than the lead pin, whereby it is easily detected whether the semiconductor IC is wrongly assembled on the circuit board. Two positioning members(50) may be installed in diagonal direction in accordance with workability. A point terminal which is electrically connected with the lead pin is formed on a terminal surface in the circuit board(20) on which the semiconductor IC is assembled. Positioning holes(54) which are coupled to the positioning members(50) of the semiconductor IC are also formed on the terminal surface.

Abstract translation: 目的：提供一种用于确定表面安装半导体IC的位置的装置，以使表面安装半导体IC能够准确地定位在电路板上。 构成：身体包括IC芯片，电线，基片和引线接合器。 引线销突出在表面安装半导体IC的表面上，以电连接到电路板。 半导体IC是四边形的，并且在其四个边缘部分上具有定位构件（50），以通过表面贴装机将半导体IC安装在电路板上时引导要安装的位置。 定位构件（50）形成在比导引销高的位置处，由此容易检测半导体IC是否错误地组装在电路板上。 两个定位构件（50）可以根据可操作性沿对角线方向安装。 在组装有半导体集成电路的电路板（20）的端子表面上形成与引脚电连接的点端子。 耦合到半导体IC的定位构件（50）的定位孔（54）也形成在端子表面上。

公开(公告)号：KR1019900003150B1

公开(公告)日：1990-05-09

申请号：KR1019870002897

申请日：1987-03-28

Applicant: 가부시끼가이샤 도시바

Inventor： 이가라시유타카

IPC: H05K1/02

CPC classification number: H05K1/111 ,  H05K1/112 ,  H05K3/308 ,  H05K3/321 ,  H05K3/3421 ,  H05K3/42 ,  H05K2201/09472 ,  H05K2201/09509 ,  H05K2201/09845 ,  H05K2201/10189 ,  H05K2201/10704 ,  H05K2201/10871 ,  H05K2201/10901 ,  H05K2203/0455 ,  Y02P70/611 ,  Y02P70/613

Abstract: The printed circuit board includes a number of non-through holes formed in the thickness direction. Throughholes are formed in selected non-through holes. Conductive lands are formed on the periphery of the openings of the non-through holes. A second set of conductive lands are formed on the periphery of the openings of the through holes on the opposite surface and having a smaller outside diameter than the other lands. Conductors formed on the inside wall of the non-through holes and the through holes connect the conductive lands in one surface with the conductive lands in the opposite surface.

Abstract translation: 印刷电路板包括在厚度方向上形成的多个非通孔。 在选定的非通孔中形成通孔。 在非贯通孔的开口的周边形成有导电凸缘。 第二组导电焊盘形成在相对表面上的通孔的开口的周边上，并且具有比其它焊盘更小的外径。 形成在非通孔和通孔的内壁上的导体将一个表面中的导电焊盘与相对表面中的导电焊盘连接。

公开(公告)号：EP3213884A4

公开(公告)日：2018-06-20

申请号：EP15855357

申请日：2015-10-29

Applicant: KAWASAKI HEAVY IND LTD

Inventor： SANTO YOSHIKI

IPC: B25J9/22 ,  H05K1/18

CPC classification number: H05K1/181 ,  B25J9/16 ,  H05K1/18 ,  H05K2201/10212 ,  H05K2201/10545 ,  H05K2201/10704

Abstract: A control circuit board 1 includes a first and second elements 5, 6 on each surface of a board member 4. The first and the second elements 5, 6 respectively have first and third edge portions 9, 11 which are opposite to each other and second and fourth edge portions 10, 12 which are opposite to each other. A plurality of signal input pins I1 to I5 are provided to the first edge portion 9, a plurality of signal output pins O1 to 05 are provided to the third edge portion 11, a plurality of between-element communication input pins A1 ˆ¼ to A5 are provided to the second edge portion 10, and a plurality of between-element communication output pins B1 to B5 are provided to the fourth edge portion 12, respectively. A common signal is input to the first and second elements 5, 6 and a communication is performed between the first element 5 and the-second element 6. Loss of control function can be surely prevented while suppressing enlargement of the board and increase of development/production cost.

公开(公告)号：EP3213884A1

公开(公告)日：2017-09-06

申请号：EP15855357.8

申请日：2015-10-29

Applicant: Kawasaki Jukogyo Kabushiki Kaisha

Inventor： SANTO, Yoshiki

IPC: B25J9/22 ,  H05K1/18

CPC classification number: H05K1/181 ,  B25J9/16 ,  H05K1/18 ,  H05K2201/10212 ,  H05K2201/10545 ,  H05K2201/10704

Abstract: A control circuit board 1 includes a first and second elements 5, 6 on each surface of a board member 4. The first and the second elements 5, 6 respectively have first and third edge portions 9, 11 which are opposite to each other and second and fourth edge portions 10, 12 which are opposite to each other. A plurality of signal input pins I1 to I5 are provided to the first edge portion 9, a plurality of signal output pins O1 to 05 are provided to the third edge portion 11, a plurality of between-element communication input pins A1 ∼ to A5 are provided to the second edge portion 10, and a plurality of between-element communication output pins B1 to B5 are provided to the fourth edge portion 12, respectively. A common signal is input to the first and second elements 5, 6 and a communication is performed between the first element 5 and the-second element 6. Loss of control function can be surely prevented while suppressing enlargement of the board and increase of development/production cost.

Abstract translation: 控制电路板1包括位于板构件4的每个表面上的第一元件5和第二元件6.第一元件5和第二元件6分别具有彼此相对的第一边缘部分9和第三边缘部分11， 和彼此相对的第四边缘部分10,12。 多个信号输入引脚I1至I5被提供给第一边缘部分9，多个信号输出引脚O1至05被提供给第三边缘部分11，多个元件间通信输入引脚A1〜A5被 提供给第二边缘部分10，并且多个元件间通信输出引脚B1至B5分别提供给第四边缘部分12。 共同的信号被输入到第一和第二元件5,6，并且在第一元件5和第二元件6之间进行通信。在抑制电路板的扩大和增加显影/ 生产成本。

公开(公告)号：EP1961041A2

公开(公告)日：2008-08-27

申请号：EP06835649.2

申请日：2006-12-04

Applicant: Nederlandse Organisatie voor Toegepast-Natuurwetenschappelijk Onderzoek TNO

Inventor： SMULDERS, Edwin, Johannes, Theodorus ,  PUIK, Erik, Christian, Nicolaas

IPC: H01L21/60

CPC classification number: H05K3/321 ,  B81C99/002 ,  B81C2203/032 ,  H01L21/6835 ,  H01L2224/11003 ,  H01L2224/11334 ,  H01L2924/15312 ,  H05K3/28 ,  H05K2201/09472 ,  H05K2201/10704 ,  H05K2203/0178 ,  H05K2203/1105 ,  H05K2203/1121 ,  H05K2203/1446

Abstract: Method and system for depositing a frozen adhesive particle at a predetermined spot on a target body, comprising launching means (13) which are arranged to launch the particle (2) in its frozen form towards the target body (3, 4) via a movement path (14) through a gap (15) between the launching means and the target body. The medium in the gap may have a temperature above the adhesive particle's melting temperature. The launching means may be arranged to launch the particle at a high speed. The launching means and the target body may have a geometry causing that the movement path is substantially vertical or substantially horizontal.

公开(公告)号：EP0898857A4

公开(公告)日：2005-06-01

申请号：EP97917633

申请日：1997-03-27

Applicant: GEN DYNAMICS INF SYSTEMS INC

Inventor： PAI DEEPAK KESHAV

IPC: H01L23/498 ,  H05K3/30 ,  H05K3/34

CPC classification number: H05K3/303 ,  H01L23/49827 ,  H01L2924/0002 ,  H05K3/3426 ,  H05K2201/10424 ,  H05K2201/10704 ,  H05K2201/10946 ,  H05K2203/0769 ,  Y02P70/613 ,  Y10T29/49144 ,  Y10T29/49149 ,  Y10T29/49222 ,  Y10T29/4981 ,  H01L2924/00

Abstract: A method and apparatus are provided for connecting area grid array semiconductor chips (30) to a printed wire board (40). A compliant lead matrix (10) includes a carrier (12) and a plurality of conductive leads (14) arranged parallel to one another and secured relative to the carrier (12) in the form of a matrix. The method includes orienting a first side (16) of the lead matrix (10) to be aligned with a reciprocal matrix of conductive surface pads (36) on the area grid array semiconductor chip (30). First ends (20) of the leads are electrically connected to the conductive surface pads (36) of the area grid array chip (30). The second side (18) of the lead matrix (10) is oriented to be aligned with a reciprocal matrix of conductive surface pads (46) on a printed wire board (40). Second ends (22) of the leads (14) of the lead matrix (10) are electrically connected to the conductive surface pads (46) of the printed wire board (40) thereby establishing an electrical connection between the area grid array chip (30) and the printed wire board (40).