公开(公告)号：US20020175763A1

公开(公告)日：2002-11-28

申请号：US09821511

申请日：2001-03-30

Applicant: INSTITUTE OF MICROELECTRONICS AND OKI TECHNO CENTRE (SINGAPORE) PTE. LTD.

Inventor： Uday Dasgupta ,  Teo Tian Hwee

IPC: H03F003/45

CPC classification number: H03F3/45183 ,  H03F2203/45508 ,  H03F2203/45544 ,  H03F2203/45562 ,  H03F2203/45631 ,  H03F2203/45702

Abstract: A wide-band single-ended to differential converter (DC to 1 GHz) with very low amplitude and phase matching errors, of the order of 0.01 dB and 0.15 degrees respectively and using CMOS technology, is comprised of a first and a second stage. The very low amplitude and phase matching errors have been achieved firstly by the use of capacitive means CD across the gate and source of the first stage MOS transistor M1 with a value equal to the drain to ground (reference potential) parasitic capacitance of the tail current source device for the first stage, and secondly by using equal valued capacitive means CF1, CF2 in the second stage and setting their values to be several (5-10) times more than the gate-drain parasitic capacitances of either of the differential transistors of the second stage.

Abstract translation: 具有非常低的幅度和相位匹配误差的宽带单端到差分转换器（DC至1GHz）分别为0.01dB和0.15°，并且使用CMOS技术由第一和第二级组成。 首先通过在第一级MOS晶体管M1的栅极和源极上使用电容式装置CD，其值等于尾部电流的漏极对（参考电位）寄生电容的值，已经实现了非常低的幅度和相位匹配误差 用于第一级的源极器件，其次通过在第二级中使用相等值的电容器件CF1，CF2，并将它们的值设置为比任一个差分晶体管的栅极 - 漏极寄生电容的数倍（5-10）倍 第二阶段

公开(公告)号：US20020166838A1

公开(公告)日：2002-11-14

申请号：US09900293

申请日：2001-07-06

Applicant: Institute of Microelectronics

Inventor： Ranganathan Nagarajan

IPC: H01L021/302

CPC classification number: H01L21/3086 ,  B81B2203/033 ,  B81B2203/0384 ,  B81C1/00103 ,  G01P15/0802

Abstract: Method and apparatus for etching a tapered trench in a layer of material with a highly controllable wall profile. The layer of material has a mask adjacent a surface thereof having an opening which defines a location on the layer of material at which the trench is to be formed. Vertical etch process steps and opening enlarging process steps are then performed in an alternating manner until the trench has been etched to a desired depth. The method permits very deep tapered trenches of up to 80-100 um or more to be formed in a silicon substrate or other layer of material in a highly controllable manner. The method can be incorporated into processes for manufacturing numerous devices including MEMS devices and high power RF devices such as LDMOS and VDMOS devices.

Abstract translation: 用于蚀刻具有高度可控壁分布的材料层中的锥形沟槽的方法和装置。 材料层具有邻近其表面的掩模，该掩模具有限定在其上将形成沟槽的材料层上的位置的开口。 然后以交替的方式执行垂直蚀刻工艺步骤和开放扩大工艺步骤，直到沟槽已经被蚀刻到期望的深度。 该方法允许以高度可控的方式在硅衬底或其它材料层中形成高达80-100μm或更大的非常深的锥形沟槽。 该方法可以并入用于制造包括MEMS器件和诸如LDMOS和VDMOS器件的高功率RF器件的许多器件的工艺中。

公开(公告)号：US20020115200A1

公开(公告)日：2002-08-22

申请号：US09785588

申请日：2001-02-16

Applicant: Institute of Microelectronics

Inventor： Quanbo Zou ,  Uppili Sridhar ,  Yu Chen ,  Tit Meng Lim ,  Emmanuel Selvanayagam Zachariah ,  Tie Yan

IPC: C12M001/40

CPC classification number: B01L3/5027 ,  B01L3/5025 ,  B01L7/52 ,  B01L2200/147 ,  B01L2300/0816 ,  B01L2300/0877 ,  B01L2300/1827 ,  B01L2300/1883 ,  B01L2400/0487 ,  B01L2400/0688

Abstract: The invention describes a thermal cycler which permits simultaneous treatment of multiple individual samples in independent thermal protocols, so as to implement large numbers of DNA experiments simultaneously in a short time. The chamber is thermally isolated from its surroundings, heat flow in and out of the unit being limited to one or two specific heat transfer areas. All heating elements are located within these transfer areas and at least one temperature sensor per heating element is positioned close by. Fluid bearing channels that facilitate sending fluid into, and removing fluid from, the chamber are provided. The chambers may be manufactured as integrated arrays to form units in which each cycler chamber has independent temperature and fluid flow control. Two embodiments of the invention are described together with a process for manufacturing them.

Abstract translation: 本发明描述了一种热循环仪，其允许在独立热方案中同时处理多个单个样品，从而在短时间内同时实现大量的DNA实验。 该室与其周围热隔离，进出单元的热流限于一个或两个特定的传热区域。 所有加热元件位于这些转移区域内，每个加热元件至少有一个温度传感器靠近。 提供了便于将流体输送到腔室中并从腔室中除去流体的流体轴承通道。 腔室可以被制成集成阵列以形成其中每个循环器腔具有独立温度和流体流量控制的单元。 本发明的两个实施例与其制造方法一起被描述。

公开(公告)号：US20250149339A1

公开(公告)日：2025-05-08

申请号：US18398558

申请日：2023-12-28

Applicant: BEIJING SUPERSTRING ACADEMY OF MEMORY TECHNOLOGY ,  INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES

Inventor： Jianfeng Gao ,  Shuai Yang ,  Jinbiao Liu ,  Weibing Liu ,  Junfeng Li ,  Jun Luo ,  Jinjuan Xiang

IPC: H01L21/225 ,  H01L21/02

Abstract: A conformal boron doping method for a three-dimensional structure includes the steps of: removing a natural oxide layer on a surface of a silicon-based three-dimensional substrate; forming a buffer layer on the surface of the silicon-based three-dimensional substrate; forming a boron oxide thin film on the alumina buffer layer; covering a passivation layer on a surface of the boron oxide thin film; and driving boron impurities containing boron oxide into the silicon-based three-dimensional substrate through the buffer layer by using laser or rapid annealing, to dope the silicon-based three-dimensional substrate. Selecting suitable boron source precursors and oxidants solves the problems of difficult nucleation and inability to form a film after reaching a certain thickness for boron oxide. By selecting alumina as the passivation layer, it is possible to protect the boron oxide thin film from being damaged, and thus achieve damage-free diffusion doping during laser or rapid annealing processes.

公开(公告)号：US12293781B2

公开(公告)日：2025-05-06

申请号：US18261716

申请日：2021-01-21

Applicant: INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES

Inventor： Huai Lin ,  Guozhong Xing ,  Zuheng Wu ,  Long Liu ,  Di Wang ,  Cheng Lu ,  Peiwen Zhang ,  Changqing Xie ,  Ling Li ,  Ming Liu

IPC: G11C11/16

Abstract: The three-state spintronic device includes: a bottom electrode, a magnetic tunnel junction and a top electrode from bottom to top. The magnetic tunnel junction includes: a spin-orbit coupling layer, a ferromagnetic free layer, a barrier tunneling layer, a ferromagnetic reference layer, three local magnetic domain wall pinning centers and domain wall nucleation centers. An antisymmetric exchange interaction is modulated, and the magnetic domain wall pinning centers are embedded in an interface between a heavy metal and the ferromagnetic free layer. The magnetic domain wall nucleation centers are at two ends of the ferromagnetic free layer. A current pulse flows through the spin-orbit coupling layer to generate a spin current and the spin current is injected into the ferromagnetic free layer. Under a control of all-electrical controlled, an effective field of a spin-orbit torque drives domain wall to move and displace.

公开(公告)号：US20250133773A1

公开(公告)日：2025-04-24

申请号：US18915723

申请日：2024-10-15

Applicant: INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES

Inventor： Qingzhu ZHANG ,  Lianlian LI ,  Anyan DU ,  Huaxiang YIN ,  Lei CAO ,  Jiaxin YAO ,  Zhaohao ZHANG ,  Qingkun LI ,  Guanqiao SANG

IPC: H01L29/423 ,  H01L21/822 ,  H01L27/06 ,  H01L27/092 ,  H01L29/06 ,  H01L29/66 ,  H01L29/775 ,  H01L29/786

Abstract: The present disclosure relates to a stacked nanosheet gate-all-around device with an air spacer and a method of manufacturing a stacked nanosheet gate-all-around device with an air spacer. The stacked nanosheet gate-all-around device with the air spacer includes: a substrate with a shallow trench isolation structure on a surface of the substrate; a nanosheet stacking portion provided above the substrate, where the nanosheet stacking portion includes a stack formed by a plurality of nanosheets, and the stack formed by the nanosheets constitutes a plurality of conductive channels; a gate-all-around surrounding the nanosheet stacking portion; and a source/drain region located on two opposite sides of the nanosheet stacking portion, where an empty spacer is provided between the source/drain region and the gate-all-around, where an interior of the empty spacer is filled with at least one of air, a reducing gas, or an inert gas.

公开(公告)号：US12260911B2

公开(公告)日：2025-03-25

申请号：US18247213

申请日：2021-01-25

Applicant: INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES

Inventor： Xiaoxin Xu ,  Jie Yu ,  Danian Dong ,  Zhaoan Yu ,  Hangbing Lv

IPC: G11C13/00

Abstract: The memory circuit structure includes: a storage array, wherein the storage array includes at least two storage units; a decoder connected with a bit line and a word line of the storage array respectively; a programming circuit configured to generate a voltage pulse or a constant current pulse; a polarity switching circuit connected with the programming circuit, and configured to implement a switching between a voltage programming and a current programming of the programming circuit under a set operation and a reset operation; a detection circuit connected with the storage array, and configured to detect a detection signal of a current or a voltage corresponding to the specific storage unit in the storage array and feed back the detection signal to a control unit, wherein the detection signal output by the detection circuit is configured to enable the polarity switching circuit to switch; and the control unit.

公开(公告)号：US20250089577A1

公开(公告)日：2025-03-13

申请号：US18552786

申请日：2022-07-12

Applicant: Institute of Microelectronics, Chinese Academy of Sciences

Inventor： Guozhong Xing ,  Hao Zhang ,  Xuefeng Zhao ,  Ziwei Wang ,  Changqing Xie ,  Ming Liu

IPC: H10N50/10 ,  H10B61/00 ,  H10N30/853 ,  H10N50/01 ,  H10N50/85

Abstract: The memory cell includes: a piezoelectric substrate layer, wherein two ends of the piezoelectric substrate layer are respectively provided with a first electrode and a second electrode, and a current-free drive of skyrmion is implemented by applying a voltage to the first electrode and the second electrode; a magnetic layer on a surface of the piezoelectric substrate layer, wherein the magnetic layer is used to form a heterojunction with the piezoelectric substrate layer, and is used to generate, stabilize, and serve as a basic carrier for a movement of the skyrmion; wherein the magnetic layer includes a convex body, the convex body is configured to divide the magnetic layer into a bit region and a memory region, and the bit region is provided with a magnetic tunnel junction used to perform generation and detection functions of the skyrmion.

公开(公告)号：US20250069653A1

公开(公告)日：2025-02-27

申请号：US18947250

申请日：2024-11-14

Applicant: INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES

Inventor： Huaxiang YIN ,  Xuexiang ZHANG ,  Jiaxin YAO

IPC: G11C11/419 ,  G11C11/418 ,  H03K19/20

Abstract: The computing-in-memory circuit includes: an SRAM memory cell array including at least one memory cell connected between a first bit line and a second bit line, the memory cell includes a first inverter and a second inverter cross-coupled with each other, and the first inverter and the second inverter have an asymmetric configuration with respect to each other; a control circuit configured to: receive a first input signal, a second input signal and an operation mode control signal, process the first input signal and the second input signal according to operation mode control signal, so as to obtain a processed first input signal and a processed second input signal, and apply the processed first input signal and the processed second input signal to the first bit line and the second bit line, respectively; and a readout circuit configured to read out data stored in memory cell from the memory cell.

公开(公告)号：US20250031417A1

公开(公告)日：2025-01-23

申请号：US18543652

申请日：2023-12-18

Applicant: INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES

Inventor： Huaxiang YIN ,  Qingzhu ZHANG ,  Yadong ZHANG ,  Jiaxin YAO

IPC: H01L29/06 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/08 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775 ,  H01L29/786

Abstract: A semiconductor device and a method for manufacturing the same. The method comprise: forming a first field-effect transistor (FET) disposed on a substrate and a first isolation layer disposed on the first FET; forming a first through hole in the first isolation layer, where a metal layer is deposited in the first through hole and is electrically connected to the first FET; forming a second isolation layer, which is disposed on the first isolation layer and the metal layer; and forming a second FET which is disposed on the second isolation layer, where a second through hole is disposed in the second FET and the second isolation layer, a metal material filled in the second through hole serves as a first contact plug, and the first contact plug is electrically connected to the metal layer. The metal layer serves as a power distribution network for both FETs.