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公开(公告)号：JP5579919B2
公开(公告)日：2014-08-27
申请号：JP2013504052
申请日：2011-04-11
Inventor： シユタール，ヨハンネス , ライトゲープ，マルクス
CPC classification number: H05K1/185 , H05K1/0218 , H05K1/0298 , H05K1/115 , H05K1/14 , H05K1/144 , H05K1/181 , H05K1/186 , H05K3/4623 , H05K3/4697 , H05K2201/041 , H05K2201/042 , H05K2201/043 , H05K2201/045 , H05K2201/0723 , H05K2201/09036 , H05K2201/09072 , H05K2201/09618 , H05K2201/10 , H05K2201/10083 , H05K2201/10151 , Y10T29/49126 , Y10T29/49144
Abstract: A method for integrating a component into a printed circuit board includes the following steps: providing two completed printed circuit board elements, which more particularly consist of a plurality of interconnected plies or layers, wherein at least one printed circuit board element has a cutout or depression, arranging the component to be integrated on one of the printed circuit board elements or in the cutout of the at least one printed circuit board element, and connecting the printed circuit board elements with the component being accommodated in the cutout, as a result of which it is possible to obtain secure and reliable accommodation of a component or sensor in a printed circuit board. Furthermore, a printed circuit board of this type comprising an electronic component integrated therein is provided.
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162.发明专利Semiconductor device module, electronic circuit unit, electronic device, and method of manufacturing semiconductor device module 审中-公开半导体器件模块，电子电路单元，电子器件及制造半导体器件模块的方法
公开(公告)号：JP2011035345A
公开(公告)日：2011-02-17
申请号：JP2009183103
申请日：2009-08-06
Applicant: Fujitsu Ltd , 富士通株式会社
Inventor： TAKADA MICHIAKI
IPC: H01L25/065 , H01L25/07 , H01L25/18 , H05K3/46
CPC classification number: H05K1/189 , G11C5/04 , H01L23/5385 , H01L23/5387 , H01L25/105 , H01L2224/16 , H01L2225/06572 , H01L2225/06579 , H01L2225/1005 , H01L2225/1041 , H01L2225/107 , H01L2924/3511 , H05K1/0293 , H05K1/0295 , H05K1/141 , H05K1/144 , H05K1/147 , H05K3/0052 , H05K3/007 , H05K3/225 , H05K2201/043 , H05K2201/055 , H05K2201/09127 , H05K2201/10159 , H05K2201/10545 , H05K2201/10734 , H05K2203/1572 , H05K2203/176
Abstract: PROBLEM TO BE SOLVED: To provide a structure capable of improving reliability of a surface mount connection area of a semiconductor device. SOLUTION: A mounting substrate for surface-mounting semiconductor devices 10a and 10b includes a hollow part 102 at a location sandwiched by an area of a first substrate layer 101a, corresponding to the backside of a first mounting pad and an area of a second substrate layer 101b, corresponding to the backside of a second mounting pad. This hollow part 102 reduces the thickness of each of the mounting areas, on which the semiconductor device 10a or 10b is mounted, to reduce stresses imparted on the semiconductor devices 10a and 10b by thermal deformation from the mounting areas of the respective substrate layers, thereby improving the reliability of the connection areas between each of the semiconductor devices 10a and 10b and corresponding one of the substrate layers. COPYRIGHT: (C)2011,JPO&INPIT
Abstract translation: 要解决的问题：提供能够提高半导体器件的表面安装连接区域的可靠性的结构。 解决方案：用于表面安装半导体器件10a和10b的安装衬底包括在被第一衬底层101a的区域夹着的位置处的中空部分102，第一衬底层101a的对应于第一安装衬垫的背面和 第二基板层101b，对应于第二安装垫的背面。 该中空部102减小了安装半导体器件10a或10b的每个安装区域的厚度，以通过来自各个衬底层的安装区域的热变形来减小施加在半导体器件10a和10b上的应力，由此 提高了每个半导体器件10a和10b与相应的一个衬底层之间的连接区域的可靠性。 版权所有（C）2011，JPO＆INPIT
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公开(公告)号：JP2010183271A
公开(公告)日：2010-08-19
申请号：JP2009023967
申请日：2009-02-04
Inventor： ISHIKAWA KOJI
IPC: H04N5/225 , H04N101/00
CPC classification number: G03B17/00 , H01R12/59 , H01R12/722 , H05K1/0218 , H05K1/0245 , H05K1/147 , H05K2201/043 , H05K2201/0715 , H05K2201/09318 , H05K2201/10189
Abstract: PROBLEM TO BE SOLVED: To provide a compact and thin electronic device which mounts a plurality of external connection connectors and improves speed of communication with external devices.
SOLUTION: The electronic device has a first external connection connector (128) that is mounted on a first printed circuit board (129), and a second external connection connector (144) that is mounted on a second printed circuit board (135). The first and second external connection connectors are overlapped so that ground patterns formed on the first and second printed circuit boards are faced each other, and the electronic device is arranged in a space which is surrounded by an external member and an inner structure member.
COPYRIGHT: (C)2010,JPO&INPITAbstract translation: 要解决的问题：提供一种紧凑而薄的电子设备，其安装多个外部连接连接器并提高与外部设备的通信速度。 解决方案：电子设备具有安装在第一印刷电路板（129）上的第一外部连接连接器（128）和安装在第二印刷电路板（135）上的第二外部连接连接器（144） ）。 第一和第二外部连接连接器重叠，使得形成在第一和第二印刷电路板上的接地图案彼此面对，并且电子设备被布置在由外部构件和内部结构构件包围的空间中。 版权所有（C）2010，JPO＆INPIT
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公开(公告)号：JP2005503039A
公开(公告)日：2005-01-27
申请号：JP2003529526
申请日：2002-08-29
Applicant: シーメンス アクチエンゲゼルシヤフトSiemens Aktiengesellschaft
Inventor： ルッケ オラフ , テューツェル ベルント
CPC classification number: H01L23/3735 , H01L25/072 , H01L2224/291 , H01L2224/32225 , H05K1/0271 , H05K1/0306 , H05K3/0061 , H05K2201/043 , H05K2203/1572 , H01L2924/014
Abstract: 本発明は、平面的なセラミック基板２を有し、このセラミック基板の一方の面上には厚膜技術を用いて、同じようにセラミック基板２上に配置された、回路の電気的パワー構成素子７を電気的に接続するための導体路６が配置されている、パワー電子ユニットに関する。 このセラミック基板２は自身の他方の面で硬ろう付けによって、ヒートスプレッダとして用いられている金属性の担体要素１上に被着されている。 ここでこの担体要素１は、担体要素１を収容しているケーシングの熱伝導性ケーシング構成部分９と熱伝導性に接続されている。 セラミック基板２の方を向いていない担体要素１の面には、このセラミック基板２にほぼ対向して、回路を担っているセラミック基板２とほぼ同じ大きさを有する第２のセラミック基板４が硬ろう付けによって被着されている。
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公开(公告)号：JP2004281722A
公开(公告)日：2004-10-07
申请号：JP2003071201
申请日：2003-03-17
Applicant: Hitachi Ltd , 株式会社日立製作所
Inventor： ISHII TOSHIAKI , TSUYUNO ENJIYOU , MASUDA MITSUYASU , URUSHIBARA NORIMI , MATSUSHITA AKIRA
IPC: B60R16/02 , F02D41/00 , H01L23/31 , H01L23/473 , H01L23/495 , H01L25/04 , H01L25/18 , H05K1/02 , H05K1/14 , H05K3/00
CPC classification number: H05K1/144 , H01L23/3107 , H01L23/473 , H01L23/49531 , H01L24/45 , H01L24/48 , H01L24/49 , H01L2224/45124 , H01L2224/45144 , H01L2224/45147 , H01L2224/48091 , H01L2224/48247 , H01L2224/49171 , H01L2224/49175 , H01L2924/01078 , H01L2924/01079 , H01L2924/07811 , H01L2924/09701 , H01L2924/10253 , H01L2924/181 , H01L2924/19041 , H01L2924/19107 , H05K1/0203 , H05K3/0061 , H05K5/0082 , H05K2201/043 , H05K2201/10924 , H05K2203/049 , H01L2924/00014 , H01L2924/00 , H01L2924/00012
Abstract: PROBLEM TO BE SOLVED: To provide a resin sealed electronic circuit device that is high in heat radiation and mounting density even for the use requiring high airtightness and environmental resistance. SOLUTION: The electronic circuit device is formed by fitting at least two or more wiring boards 12 and 13 wherein electronic components are mounted on a thermal diffusion plate 14 with high thermal conductivity by means of adhesive agents 9 and 10, and the wiring boards 12 and 13, the entire thermal diffusion plate 14 and a part of an external connection terminal 8 are packaged and molded integrally by using a thermosetting resin composition 7. Thus, an inexpensive, compact, and highly reliable electronic circuit device can be provided. COPYRIGHT: (C)2005,JPO&NCIPI
Abstract translation: 要解决的问题：提供一种树脂密封的电子电路装置，其即使对于需要高气密性和耐环境性的用途，也具有高的散热和安装密度。 解决方案：电子电路装置通过装配至少两个或更多个布线板12和13而形成，其中电子部件通过粘合剂9和10以高导热性安装在热扩散板14上，并且布线 板12和13，整个热扩散板14和外部连接端子8的一部分通过使用热固性树脂组合物7一体地包装和模制。因此，可以提供廉价，紧凑且高可靠性的电子电路装置。 版权所有（C）2005，JPO＆NCIPI
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Patent Agency Ranking166.发明公开
公开(公告)号：KR1020130040796A
公开(公告)日：2013-04-24
申请号：KR1020127025593
申请日：2011-04-11
Applicant: 에이티 앤 에스 오스트리아 테크놀로지 앤 시스템테크니크 악치엔게젤샤프트
Inventor： 스타르,요한네스 , 레이트게브,마르쿠스
CPC classification number: H05K1/185 , H05K1/0218 , H05K1/0298 , H05K1/115 , H05K1/14 , H05K1/144 , H05K1/181 , H05K1/186 , H05K3/4623 , H05K3/4697 , H05K2201/041 , H05K2201/042 , H05K2201/043 , H05K2201/045 , H05K2201/0723 , H05K2201/09036 , H05K2201/09072 , H05K2201/09618 , H05K2201/10 , H05K2201/10083 , H05K2201/10151 , Y10T29/49126 , Y10T29/49144
Abstract: 인쇄회로기판에 부품(3)을 집적하는 방법에 있어서, 다음의 단계들이 제공된다. 즉, 2개의 완성된 인쇄회로기판 요소들(1,4)을 마련하는 단계로, 상기 인쇄회로기판 요소들은 보다 상세하게는 복수의 상호연결된 층들 또는 겹들(6,7,8)로 구성되고, 여기서 적어도 하나의 인쇄회로기판 요소(4)은 컷아웃 또는 오목부(10)를 포함하고, 상기 인쇄회로기판 요소들(1) 중 하나 위에 또는 상기 적어도 하나의 인쇄회로기판 요소의 상기 컷아웃 안에 집적될 부품(3)을 배치하는 단계, 및 상기 인쇄회로기판 요소들(1,4)을 상기 컷아웃(10) 안에 수용된 상기 부품(3)과 연결하는 단계로, 그 결과 인쇄회로기판에 부품 또는 센서(3)의 안전하고 신뢰할 수 있는 수용을 획득하는 것이 가능하게 된다. 나아가, 그 안에 집적되는 전자부품(3)을 포함하는 이러한 타입의 인쇄회로기판이 제공된다.
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公开(公告)号：KR1020100017408A
公开(公告)日：2010-02-16
申请号：KR1020097024714
申请日：2008-05-29
Applicant: 오컴 포트폴리오 엘엘씨
Inventor： 프젤스태드요셉씨.
CPC classification number: H05K1/144 , H01L24/73 , H01L24/82 , H01L2224/32225 , H01L2224/32245 , H01L2224/48091 , H01L2224/48227 , H01L2224/48247 , H01L2224/48465 , H01L2224/73265 , H01L2924/01063 , H01L2924/01078 , H01L2924/01079 , H01L2924/14 , H01L2924/15184 , H01L2924/3025 , H05K1/0207 , H05K1/185 , H05K3/284 , H05K3/4664 , H05K2201/042 , H05K2201/043 , H05K2201/10189 , H05K2201/10318 , H05K2201/10386 , H05K2201/1056 , H05K2203/1316 , H01L2924/00014 , H01L2924/00 , H01L2924/00012
Abstract: The present invention provides an electronic assembly 400 and a method for its manufacture 800, 900, 1000 1200, 1400, 1500, 1600, 1700. The assembly 400 uses no solder. Components 406, or component packages 402, 802, 804, 806 with I/O leads 412 are placed 800 onto a planar substrate 808. The assembly is encapsulated 900 with electrically insulating material 908 with vias 420, 1002 formed or drilled 1000 through the substrate 808 to the components' leads 412. Then the assembly is plated 1200 and the encapsulation and drilling process 1500 repeated to build up desired layers 422, 1502, 1702. Assemblies may be mated 1800. Within the mated assemblies, items may be inserted including pins 2202a, 2202b, and 2202c, mezzanine interconnection devices 2204, heat spreaders 2402, and combination heat spreaders and heat sinks 2602. Edge card connectors 2802 may be attached to the mated assemblies.
Abstract translation: 本发明提供电子组件400及其制造方法800,900,10001200,1400,1500,1600,1700。组件400不使用焊料。 具有I / O引线412的组件406或组件封装402,802,804,806被放置在800平面衬底808上。该组件被电绝缘材料908封装，电绝缘材料908具有穿过衬底形成或钻孔1000的通孔420,1002。 808到组件引线412.然后组件被电镀1200，并且重复进行封装和钻孔工艺1500以构建所需的层422,1502,1702。组件可以配合1800.在配合的组件内，物品可以被插入，包括销 2202a，2202b和2202c，夹层互连设备2204，散热器2402以及散热器和散热器2602组合。边缘卡连接器2802可以附接到配合的组件。
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公开(公告)号：KR1020040106326A
公开(公告)日：2004-12-17
申请号：KR1020047015943
申请日：2003-04-02
Applicant: 소니 주식회사
IPC: H04B1/08
CPC classification number: H05K9/006 , H04B1/005 , H04B1/08 , H04B1/18 , H04N5/50 , H04N5/64 , H04N21/4263 , H04N21/6143 , H05K1/0218 , H05K1/0237 , H05K1/144 , H05K2201/043 , H05K2201/0715 , H05K2201/0723
Abstract: 위성 방송 등의 방송을 수신하는 복수의 튜너를 구비하는 수신 장치로서, 영상 신호 및/또는 음성 신호를 소정 형식으로 변조한 방송파가 입력되는 입력 단자(11)와, 방송파로부터 소정의 주파수 대역에 포함되는 영상 신호 및/또는 음성 신호를 선택하기 위한 메인 회로(12)가 배치된 마운트층(13)을 갖는 튜너 회로(1)에 있어서의 마운트층(13)의 메인 회로(12)가 배치되는 면의 반대면에 제1 유전체층(14)을 개재하여 제1 접지층(15)을 구비하고, 또한 제2 유전체층을 개재하여 제2 접지층(17)을 구비함으로써 복수의 튜너 간의 상호 간섭을 저감할 수 있다.
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公开(公告)号：JP5175746B2
公开(公告)日：2013-04-03
申请号：JP2008554156
申请日：2007-02-14
Applicant: エルジー イノテック カンパニー リミテッド
Inventor： ウク リー、ヒョン
CPC classification number: H05K3/361 , H01L2224/48091 , H05K1/0393 , H05K3/064 , H05K3/281 , H05K3/323 , H05K3/4611 , H05K3/4635 , H05K3/4691 , H05K3/4694 , H05K2201/0191 , H05K2201/0355 , H05K2201/043 , H05K2201/09127 , H05K2201/09972 , H01L2924/00014
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公开(公告)号：JP4737286B2
公开(公告)日：2011-07-27
申请号：JP2008505035
申请日：2007-02-26
Applicant: パナソニック株式会社
IPC: G06K19/077 , G06K19/07 , H01Q7/06 , H05K1/14 , H05K3/36
CPC classification number: H01Q1/22 , G06K19/07732 , G06K19/07749 , H01Q7/06 , H05K1/0218 , H05K1/144 , H05K1/148 , H05K1/16 , H05K2201/043 , H05K2201/086 , Y10T29/4913
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