公开(公告)号：EP1878326A2

公开(公告)日：2008-01-16

申请号：EP06740704.9

申请日：2006-04-05

Applicant: FCI

Inventor： MINICH, Steven ,  SMITH, Stephen, B. ,  MORLION, Danny

IPC: H05K1/00

CPC classification number: H01R12/737 ,  H01R12/716 ,  H01R12/724 ,  H01R13/6585 ,  H05K1/0219 ,  H05K1/0237 ,  H05K1/114 ,  H05K1/115 ,  H05K1/14 ,  H05K3/308 ,  H05K3/429 ,  H05K2201/044 ,  H05K2201/09236 ,  H05K2201/09627 ,  H05K2201/10189 ,  H05K2201/1059 ,  H05K2201/10659

Abstract: An orthogonal backplane connector systems having midplane footprints that provide for continuity of impedance and signal integrity through the midplane and allow for the same connector to be coupled to either side of the midplane. This design creates an orthogonal interconnect without taking up unnecessary PCB real estate. The midplane circuit board may include a first differential signal pair of electrically conductive vias disposed in a first direction, and a second differential signal pair of electrically conductive vias disposed in a second direction that is generally orthogonal to the first direction.

公开(公告)号：EP1487060A3

公开(公告)日：2007-11-07

申请号：EP04394034.5

申请日：2004-06-11

Applicant: Nortel Networks Limited

Inventor： Kwong, Herman ,  Difilippo, Luigi ,  Wyrzykowska, Aneta

IPC: H05K3/36 ,  H01R12/06

CPC classification number: H01R12/523 ,  H01R12/57 ,  H01R13/642 ,  H01R13/665 ,  H05K3/3436 ,  H05K3/3447 ,  H05K3/365 ,  H05K3/368 ,  H05K3/429 ,  H05K2201/09472 ,  H05K2201/09536 ,  H05K2201/10659 ,  H05K2203/061 ,  Y10T409/300112 ,  Y10T409/300616

Abstract: A circuit device for interconnecting first and second multilayer circuit boards is described herein. The first multilayer circuit board may include a first plurality of electrically conductive vias of varying depths and the second multilayer circuit board may include a second plurality of electrically conductive vias. The circuit device comprises a first plurality of pins located on a first side of the circuit device corresponding to the first plurality of electrically conductive vias of the first multilayer circuit board, each pin having a length compatible with a depth of a respective one of the first plurality of electrically conductive vias of the first multilayer circuit board. The circuit device further comprises a second plurality of pins located on a second side of the circuit device corresponding to the second plurality of electrically conductive vias of the second multilayer circuit board.

公开(公告)号：EP1775817A1

公开(公告)日：2007-04-18

申请号：EP05743629.7

申请日：2005-05-24

Applicant: Sumitomo Wiring Systems, Ltd.

Inventor： HAYAKAWA, Tatsuya, SUMITOMO WIRING SYSTEMS, LTD ,  OKA, Tatsuya, SUMITOMO WIRING SYSTEMS, LTD

IPC: H02G3/16

CPC classification number: H05K7/026 ,  H01R9/2425 ,  H01R9/2466 ,  H05K1/144 ,  H05K3/3447 ,  H05K2201/10189 ,  H05K2201/10303 ,  H05K2201/10659

Abstract: Three printed boards are stored in a case, and a relay connector (10) for connecting the three printed boards is mounted on the second printed board (50) at the middle position. The relay connector (10) is provided with a first terminal storing part (14), which is long in a vertical direction, and a short second terminal storing part (15). The relay connector connects a terminal pin (41) of the first printed board (40) at an upper position with a terminal pin (61) of the third printed board (60) at a lower position, via a long first relay terminal (20) stored in the first terminal storing part (14), while connecting a terminal pin (42) of the first printed board and/or the terminal pin of the third printed board with a conductor (53) of the second printed board, via a short second relay terminal (21) stored in the second terminal storing part (15).

Abstract translation: 三个印刷电路板被存储在壳体中，并且用于连接三个印刷电路板的中继连接器（10）在中间位置安装在第二印刷电路板（50）上。 中继连接器（10）设置有在垂直方向上长的第一端子存储部（14）和短的第二端子存储部（15）。 继电器连接器通过长的第一中继端子（20）将位于上位置的第一印刷电路板（40）的端子引脚（41）与第三印刷电路板（60）的端子引脚（61） ）存储在第一端子存储部分（14）中，同时通过第一印刷电路板的导体（53）将第一印刷电路板的端子引脚（42）和/或第三印刷电路板的端子引脚连接到第二印刷电路板的导体（53） 短的第二中继终端（21）存储在第二终端存储部（15）中。

公开(公告)号：EP0892432B1

公开(公告)日：2004-12-08

申请号：EP98105813.4

申请日：1998-03-30

Applicant: TYCO Electronics Logistics AG

Inventor： Rehnelt, Karl ,  Templin, Frank

IPC: H01L23/498 ,  H01L25/16 ,  H01R12/32 ,  H05K3/30

CPC classification number: H05K3/366 ,  H01L23/49811 ,  H01L2924/0002 ,  H05K3/305 ,  H05K2201/10386 ,  H05K2201/10659 ,  H05K2203/167 ,  H01L2924/00

公开(公告)号：EP0844811B1

公开(公告)日：2004-09-22

申请号：EP97850147.6

申请日：1997-10-24

Applicant: Infineon Technologies AG

Inventor： Hellgren, Eva ,  Eriksson, Mats

IPC: H05K7/08 ,  H05K13/04

CPC classification number: H05K3/366 ,  H05K3/303 ,  H05K13/046 ,  H05K2201/10386 ,  H05K2201/10454 ,  H05K2201/10568 ,  H05K2201/10659 ,  H05K2201/10696 ,  H05K2203/167 ,  Y02P70/613

公开(公告)号：EP0991141A2

公开(公告)日：2000-04-05

申请号：EP99650051.8

申请日：1999-06-21

Applicant: HIROSE ELECTRIC CO., LTD.

Inventor： Morita, Shigehiro, c/o Hirose Electric Co.,Ltd.

IPC: H01R12/22

CPC classification number: H05K3/341 ,  H01R12/716 ,  H05K3/3426 ,  H05K2201/09781 ,  H05K2201/10189 ,  H05K2201/10659 ,  H05K2203/306 ,  Y02P70/613

Abstract: The connector comprises a housing (7) having a solderable portion, a reinforcing metal member (5) movably attached to the housing such that it is vertically movable when it is soldered to the board (12). The reinforcing metal member and the solderable portion are provided so as to form a gap (14) between them, which permits soldering by capillary effects.

公开(公告)号：EP0767495A2

公开(公告)日：1997-04-09

申请号：EP96119436.2

申请日：1992-06-16

Applicant: FUJITSU LIMITED

Inventor： The designation of the inventor has not yet been filed

IPC: H01L23/495 ,  H05K1/18 ,  H01L25/065

CPC classification number: H05K1/0203 ,  H01L23/49555 ,  H01L23/49568 ,  H01L23/49575 ,  H01L23/49582 ,  H01L2224/05554 ,  H01L2224/45144 ,  H01L2224/48247 ,  H01L2224/49175 ,  H01L2924/00014 ,  H01L2924/181 ,  H01L2924/19107 ,  H05K1/181 ,  H05K2201/10166 ,  H05K2201/10454 ,  H05K2201/10469 ,  H05K2201/1053 ,  H05K2201/10659 ,  Y02P70/611 ,  H01L2224/45099 ,  H01L2924/00 ,  H01L2924/00012

Abstract: A semiconductor device comprises a first and a second semiconductor chip that are separate from each other, a first resin package body for accomodating said first semiconductor chip and a second resin package body for accomodating said second semiconductor chip. Each of the resin package bodies comprises groups of interconnection leads at the lower edge thereof and a heat dissipation lead connecting the first resin package body and the second resin package body with each other. The heat sink part is projecting outwardly from the top edge of the first and second resin package body so as to bridge and connect the first and second resin package bodies. The semiconductor device is held upright on a substrate and is suitable for the mounting on the substrate by the surface mounting technology. Simultaneously, the device achieves an efficient cooling by the heat sink part that connects the first and second resin package bodies.

Abstract translation: 半导体器件包括彼此分开的第一和第二半导体芯片（76,77），用于容纳所述第一半导体芯片的第一树脂封装体（71）和用于容纳所述第二半导体芯片的第二树脂封装体（72） 半导体芯片。 每个树脂封装体包括在其下边缘处的一组互连引线（74,75）和将第一树脂封装体和第二树脂封装体彼此连接的散热引线（73）。 散热部件（73c）从第一和第二树脂封装主体的顶部边缘向外突出，从而桥接和连接第一和第二树脂封装体。 半导体器件直立地保持在基板（19）上，并且适用于通过表面安装技术安装在基板上。 同时，该装置通过连接第一和第二树脂封装体的散热部实现有效的冷却。

公开(公告)号：EP0760164A1

公开(公告)日：1997-03-05

申请号：EP96911346.0

申请日：1996-03-20

Applicant: National Semiconductor Corporation

Inventor： CHILLARA, Satya ,  MOSTAFAZADEH, Shahram

IPC: H01L23 ,  H05K3

CPC classification number: H01L23/49861 ,  H01L23/3121 ,  H01L23/49517 ,  H01L23/4985 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/05553 ,  H01L2224/05554 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48247 ,  H01L2224/49109 ,  H01L2224/49175 ,  H01L2224/49433 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01027 ,  H01L2924/01052 ,  H01L2924/01057 ,  H01L2924/01068 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/15153 ,  H01L2924/1517 ,  H01L2924/15173 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/19107 ,  H01L2924/30107 ,  H05K3/341 ,  H05K2201/10659 ,  H05K2201/10689 ,  H05K2201/10734 ,  Y02P70/613 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2924/00012

Abstract: An integrated circuit assembly (30) is disclosed herein. The assembly includes a dielectric substrate (32) defining a predetermined array of electrically conductive traces (40) and an array of solder balls (42) electrically connected to the traces (40). An integrated circuit chip (44) having a series of input/output pads is supported on the substrate (36). In one embodiment, a plurality of leadframe leads (48) are supported by the substrate (36) in electrical isolation from and over the conductive traces (40). First and second series of bonding wires (56, 58) electrically connect certain ones of the input/output pads on the IC chip (44) to the leadframe leads (48) and conductive traces (40). In other embodiments, one or more electrically isolated conductive layers (142, 144) are supported by the dielectric substrate (122) over the traces (128) and leadframe leads (130). The integrated circuit assembly (120), in accordance with any of these embodiments, provides a very high density electrical interconnection arrangement for the IC chip (132) while retaining a small package footprint.

Abstract translation: 本文公开了集成电路组件。 组件包括限定预定排列的导电迹线的电介质基片和电连接到迹线的焊球阵列。 具有一系列输入/输出焊盘的集成电路芯片被支撑在基板上。 在一个实施例中，多个引线框引线由导电迹线与导电迹线电绝缘而被基板支撑。 第一和第二系列接合线将IC芯片上的某些输入/输出焊盘电连接到引线框引线和导电迹线。 在其他实施例中，一个或多个电隔离的导电层由电介质基板支撑在迹线和引线框引线上。 根据这些实施例中的任何一个的集成电路组件为IC芯片提供非常高密度的电互连布置，同时保持小的封装封装。

公开(公告)号：EP0682366A3

公开(公告)日：1996-03-06

申请号：EP95107226.3

申请日：1995-05-12

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Russell, Ernest ,  Wallace, James S. ,  Baudouin, Daniel

IPC: H01L23/32 ,  H01L23/48 ,  H05K1/18 ,  H01L25/10 ,  H01L23/495 ,  H05K3/30

CPC classification number: H05K1/181 ,  H01L23/32 ,  H01L23/49555 ,  H01L25/105 ,  H01L2225/1029 ,  H01L2225/107 ,  H01L2225/1082 ,  H01L2924/0002 ,  H05K3/303 ,  H05K2201/10454 ,  H05K2201/10545 ,  H05K2201/10568 ,  H05K2201/10659 ,  H05K2201/10696 ,  H05K2203/167 ,  Y02P70/611 ,  Y02P70/613 ,  H01L2924/00

Abstract: Two flat packages (110, 111) are arranged to achieve a mirrored footprint by employing guides (100), which are positioned within a mounting aperture a printed circuit board. The flat packages include leads (120,121) which extend from the edge of the flat package. A semiconductor chip is encapsulated by the flat packages.

公开(公告)号：EP0510869A3

公开(公告)日：1993-04-28

申请号：EP92303386.4

申请日：1992-04-15

Applicant: THE WHITAKER CORPORATION

Inventor： Korsunsky, Iosif ,  Grabbe, Dimitry

IPC: H01R23/70 ,  H01R23/68

CPC classification number: H01R12/716 ,  H01R12/57 ,  H01R12/585 ,  H01R12/737 ,  H01R13/658 ,  H05K1/117 ,  H05K3/3405 ,  H05K3/429 ,  H05K2201/09163 ,  H05K2201/10189 ,  H05K2201/1034 ,  H05K2201/10401 ,  H05K2201/10659 ,  H05K2201/10916

Abstract: An electrical connector (16) has first terminals (50) which are surface mounted to respective sides of a substrate (12) and second terminals (70) which extend through an edge surface of the substrate (12) to make electrical connection to an opening provided in the substrate. As the connector (16) is mated to the edge of the substrate (12), the connector (16) occupies a minimal space on the substrate (12).