公开(公告)号：EP4386859A1

公开(公告)日：2024-06-19

申请号：EP23204762.1

申请日：2023-10-20

Applicant: GlobalFoundries U.S. Inc.

Inventor： Sharma, Santosh ,  Levy, Mark D.

IPC: H01L29/778 ,  H01L29/10 ,  H01L27/06 ,  H01L29/417 ,  H01L29/20

CPC classification number: H01L29/7786 ,  H01L29/2003 ,  H01L29/1066 ,  H01L29/41766 ,  H01L27/0605 ,  H01L27/085 ,  H01L21/8252

Abstract: A disclosed structure includes an enhancement mode high electron mobility transistor (HEMT). The HEMT includes a barrier layer (103) with a thick portion (103T) positioned laterally between thin portions (103t) and a gate. The gate includes a semiconductor layer (132) (e.g., a P-type III-V semiconductor layer) on the thick portion of the barrier layer and having a thick portion (132T) positioned laterally between thin portions (132t). The gate also includes a gate conductor layer (133) on and narrower than the thick portion of the semiconductor layer, so end walls of the gate are stepped. Thin portions of the barrier layer near these end walls minimize or eliminate charge build up in a channel layer below. To block current paths around the gate, isolation regions can be below the thin portions of the barrier layer offset from the semiconductor layer. The structure can further include alternating e-mode and d-mode HEMTs. Also disclosed are associated method embodiments.

公开(公告)号：EP4325188A3

公开(公告)日：2024-06-19

申请号：EP23181591.1

申请日：2023-06-27

Applicant: GlobalFoundries U.S. Inc.

Inventor： ZHAO, Zhixing ,  CHEN, Yiching ,  RESTREPO, Oscar D.

IPC: G01K7/16 ,  H01L23/34

CPC classification number: G01K7/16

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to built-in temperature sensors and methods of manufacture. The structure includes: at least one active gate structure; and a built-in temperature sensor adjacent to and on a same device level as the at least one active gate structure, the built-in temperature sensor further includes force lines and sensing lines.

公开(公告)号：EP4383334A1

公开(公告)日：2024-06-12

申请号：EP23197836.2

申请日：2023-09-18

Applicant: GlobalFoundries U.S. Inc.

Inventor： Krishnasamy, Rajendran ,  Ellis-Monaghan, John J. ,  Adusumilli, Siva P. ,  Hazbun, Ramsey M.

IPC: H01L27/146 ,  H01L31/105 ,  H01L31/028 ,  H01L31/0352

CPC classification number: H01L31/105 ,  H01L31/028 ,  H01L31/035281 ,  H01L27/1461 ,  H01L27/1446 ,  H01L27/14612

Abstract: A photodiode and a related method of manufacture are disclosed. The photodiode (100) includes a transfer gate (122) and a floating diffusion (124) adjacent to the transfer gate. In addition, the photodiode includes an upper terminal (112); an intrinsic semiconductor region (114) in contact with the upper terminal, the intrinsic semiconductor region in a trench (130) in a substrate (132) adjacent to the transfer gate; and a lower terminal (116) in contact with the intrinsic semiconductor region. An insulator layer (140) is along an entirety of a sidewall (142) of the intrinsic semiconductor region and between the intrinsic semiconductor region and the transfer gate. A p-type well (154, 156) may also optionally be between the insulator layer and the transfer gate.

公开(公告)号：EP4383328A1

公开(公告)日：2024-06-12

申请号：EP23201733.5

申请日：2023-10-05

Applicant: GlobalFoundries U.S. Inc.

Inventor： Mulfinger, George Robert ,  Mala, Selina A. ,  Pandey, Shesh Mani ,  Rosenfeld, Adam S. ,  Bhuyian, Md Nasir Uddin

IPC: H01L23/525

CPC classification number: H01L23/5256

Abstract: A one-time programmable (OTP) fuse includes a trench isolation; a gate metal layer over the trench isolation; and a PN junction over the gate metal layer. More particularly, the OTP fuse may include a first terminal including a highly doped n-type polysilicon layer over the trench isolation, and a second terminal including a highly doped p-type polysilicon layer over the trench isolation. The highly doped n-type polysilicon layer contacts the highly doped p-type polysilicon layer, creating a PN junction and a fuse link defined in a portion of the gate metal layer between the trench isolation and the PN junction. The gate metal layer has a uniform thickness that allows better dimension control of the fuse link to reduce fuse programming current variability.

公开(公告)号：EP4379811A2

公开(公告)日：2024-06-05

申请号：EP23199260.3

申请日：2023-09-25

Applicant: GlobalFoundries U.S. Inc.

Inventor： SHARMA, Santosh ,  KRISHNASAMY, Rajendran ,  KANTAROVSKY, Johnatan A.

IPC: H01L29/778 ,  H01L21/337 ,  H01L29/06 ,  H01L29/40 ,  H01L29/10 ,  H01L29/20

CPC classification number: H01L29/7786 ,  H01L29/2003 ,  H01L29/1066 ,  H01L29/404 ,  H01L29/0657 ,  H01L29/66462

Abstract: Semiconductor structures and, more particularly, a high-electron-mobility transistor and methods of manufacture thereof are disclosed. The structure includes: a gate structure (18, 22, 28); and a channel region (14, 16) under the gate structure, the channel region having a first portion including a first thickness and a second portion having a second thickness greater than the first thickness, the second portion being positioned remotely from the gate structure.

公开(公告)号：EP4358124A1

公开(公告)日：2024-04-24

申请号：EP23195573.3

申请日：2023-09-06

Applicant: GlobalFoundries U.S. Inc.

Inventor： MULFINGER, George R.

IPC: H01L21/8238 ,  H01L21/84 ,  H01L27/092 ,  H01L27/12 ,  H01L29/10

CPC classification number: H01L27/092 ,  H01L21/823807 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/1054 ,  H01L21/823878

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a device with a laterally graded channel region and methods of manufacture. The structure includes a PFET region with a laterally graded semiconductor channel region under a gate material.

公开(公告)号：EP4354733A2

公开(公告)日：2024-04-17

申请号：EP23196216.8

申请日：2023-09-08

Applicant: GlobalFoundries U.S. Inc.

Inventor： Sharma, Santosh

IPC: H03K17/16 ,  H03K17/687

CPC classification number: H03K17/162 ,  H03K17/165 ,  H03K17/163 ,  H03K17/168 ,  H03K17/6871 ,  H03K2017/687520130101

Abstract: Disclosed are circuits for controlling slew rate of a transistor during switching. Each circuit includes a first transistor (e.g., a gallium nitride (GaN)-based high electron mobility transistor (HEMT) or metal-insulator-semiconductor HEMT (MISHEMT)), a capacitor, and a second transistor. The first transistor includes a first gate connected to a pad for receiving a pulse-width modulation (PWM) signal, a first drain region connected to a first plate of the capacitor, and a first source region. The second transistor includes a second gate connected to a second plate of the capacitor, a second drain region, and a second source region and is connected to both the pad and the first transistor. The connection between the first and second transistors varies depending on whether the first transistor is an enhancement or depletion mode device and on whether the slew rate control is employed for on state or off state switching.

公开(公告)号：EP4354443A2

公开(公告)日：2024-04-17

申请号：EP23187997.4

申请日：2023-07-27

Applicant: GlobalFoundries U.S. Inc.

Inventor： Gopinath, Venkatesh P. ,  Parvarandeh, Pirooz

IPC: G11C29/02

CPC classification number: G11C29/028

Abstract: Disclosed structures include a partitioned memory architecture, which includes single resistor or dual resistor memory elements, which is configured for in-memory pipeline processing with minimal local IR drops, and which further includes additional circuitry to facilitate calibration processing. In some embodiments, the additional circuitry enables calibration processing when in-memory pipeline processing is paused. In these embodiments, the same bitlines and data sensing elements used for in-memory pipeline processing are also used for calibration processing. In other embodiments, the additional circuitry enables calibration processing concurrent with in-memory pipeline processing. In these embodiments, the additional circuitry includes duplicate pairs of memory elements with programmable resistors that can be connected to the operational circuitry for in-memory pipeline processing, to the calibration circuitry (including calibration-specific sense lines and sensing elements) for calibration processing, or to neither such that one memory element of the duplicate pair always remains operational allowing the other to undergo calibration.

公开(公告)号：EP4354436A1

公开(公告)日：2024-04-17

申请号：EP23187989.1

申请日：2023-07-27

Applicant: GlobalFoundries U.S. Inc.

Inventor： Gopinath, Venkatesh P. ,  Parvarandeh, Pirooz

IPC: G11C7/10 ,  G06F7/544 ,  G06N3/065 ,  G11C7/12 ,  G11C11/54 ,  G11C11/56 ,  G11C13/00 ,  G11C27/02

CPC classification number: G11C7/1006 ,  G06F7/5443 ,  G06N3/065 ,  G11C11/54 ,  G11C11/56 ,  G11C13/0004 ,  G11C13/0026 ,  G11C13/0028 ,  G11C13/003 ,  G11C13/004 ,  G11C7/1084 ,  G11C7/12 ,  G11C27/026 ,  G11C2213/7720130101 ,  G11C7/1039

Abstract: A structure for in-memory processing includes memory banks arranged in columns and rows, each bank having bank input nodes, at least one bitline, and cells arranged in a column and connected to corresponding bank input nodes, respectively, and to the bitline(s). Each cell includes layer-specific memory elements, which are individually programmable to store layer-specific weight values and individually connectable (e.g., by switches) to the corresponding bank input node and the bitline(s). The initial memory banks in each row also include track-and-hold devices (THs) connected to the bank input nodes. For each iteration of in-memory processing, the outputs from one processing layer are feedback to pre-designated THs for use as inputs for the next processing layer, the appropriate layer-specific memory elements in the cells are connected to the corresponding bank input nodes and bitline(s), and output(s) for the next processing layer are generated.

公开(公告)号：EP4346101A1

公开(公告)日：2024-04-03

申请号：EP23190154.7

申请日：2023-08-08

Applicant: GlobalFoundries U.S. Inc.

Inventor： SHARMA, Santosh

IPC: H03K5/156 ,  H03K17/30

Abstract: The present disclosure relates to a circuit and, more particularly, to comparator circuits used with a depletion mode device and methods of operation. The circuit includes: a comparator; a transistor connected to an output of the comparator; and a depletion mode device connected to ground and comprising a control gate connected to the transistor.