公开(公告)号：WO2004102634A2

公开(公告)日：2004-11-25

申请号：PCT/US2004/009285

申请日：2004-04-14

Applicant: THE REGENTS OF THE UNIVERSITY OF CALIFORNIA ,  MACDONALD, Noel, C. ,  AIMI, Marco, F.

Inventor： MACDONALD, Noel, C. ,  AIMI, Marco, F.

IPC: H01L

CPC classification number: C23F4/00 ,  B81C1/00492 ,  B81C2201/0132

Abstract: Metal MEMS structures are fabricated from metal substrates, preferably titanium, utilizing micromachining processes with a new deep etching procedure to provide released microelectromechanical devices. The deep etch procedure includes metal anisotropic reactive ion etching utilizing repetitive alternating steps of etching and side wall protection. Variations in the timing of the etching and protecting steps produces walls of different roughness and taper. The metal wafers can be macomachined before forming the MEMS structures, and the resulting wafers can be stacked and bonded in packages.

Abstract translation: 金属MEMS结构由金属基底（优选钛）制成，利用微加工工艺和新的深刻蚀工艺来提供释放的微机电装置。 深蚀刻程序包括利用重复的蚀刻和侧壁保护的交替步骤的金属各向异性反应离子蚀刻。 蚀刻和保护步骤的时间变化产生不同粗糙度和锥度的壁。 在形成MEMS结构之前，金属晶片可以被加工，并且所得到的晶片可以堆叠并结合成封装。

公开(公告)号：WO2003055791A2

公开(公告)日：2003-07-10

申请号：PCT/US2002/029853

申请日：2002-10-11

Applicant: APPLIED MATERIALS, INC.

Inventor： CHINN, Jeffrey, D. ,  SOUKANE, Sofiane

IPC: B81C1/00

CPC classification number: B81C1/00928 ,  B81C2201/0132

Abstract: A two-step method of releasing microelectromechanical devices from a substrate is disclosed. The first step comprises isotropically etching a silicon oxide layer sandwiched between two silicon-containing layers with a gaseous hydrogen fluoride-water mixture, the overlying silicon layer to be separated from the underlying silicon layer or substrate for a time sufficient to form an opening but not to release the overlying layer, and the second step comprises adding a drying agent to substitute for moisture remaining in the opening and to dissolve away any residues in the opening that can cause stiction.

Abstract translation: 公开了一种从基板释放微机电装置的两步法。 第一步包括用夹杂在两个含硅层之间的氧化硅层与氟化氢 - 水气体混合物进行各向同性蚀刻，所述上层硅层将与下面的硅层或衬底分离足以形成开口但不 以释放上覆层，第二步骤包括加入干燥剂以代替残留在开口中的水分，并溶解开口中可能导致静电的任何残留物。

公开(公告)号：WO00015544A1

公开(公告)日：2000-03-23

申请号：PCT/EP1999/006685

申请日：1999-09-10

IPC: B81B1/00 ,  B82B1/00 ,  B82B3/00 ,  G01Q60/06 ,  G01Q60/18 ,  G01Q60/22 ,  G01Q60/38 ,  G01Q70/08 ,  G02B27/58 ,  H01J9/02 ,  H01J37/09 ,  H01L21/306 ,  G01B7/34

CPC classification number: B81C1/00087 ,  B81B2201/047 ,  B81B2203/0361 ,  B81C2201/0132 ,  G01Q60/06 ,  G01Q60/22 ,  G01Q60/38 ,  G02B27/58 ,  H01J9/02 ,  H01J37/09

Abstract: Es wird ein Verfahren zur Herstellung einer Apertur (10) in einem Halbleitermaterial (12) mit folgenden Schritten beschrieben: Bereitstellen eines Halbleiterwafers (14), beispielsweise eines (100)-orientierten Siliziumwafers mit einer Oberfläche (16) und einer Unterfläche (18), Erzeugen einer Vertiefung (20) mit einer Seitenwand (22) in der Oberfläche (16) des Halbleiterwafers (14) durch partielles Anätzen der Oberfläche (16), wobei die Vertiefung (20) einen der Unterfläche (18) zugewandten, geschlossenen Bodenbereich (24) bevorzugt mit insbesondere einer konvexen oder insbesondere einer konkaven Ecke oder Kante oder dergleichen Krümmung aufweist. Nach Aufbringen einer Oxidschicht (26) auf dem Halbleitermaterial (12) wenigstens im Bereich der Vertiefung (20) durch Oxidation des Halbleitermaterials (12), wobei die Oxidschicht (26) im Bodenbereich (24) bevorzugt eine Inhomogenität (28) aufweist, wird das Halbleitermaterial (14) an der Unterfläche (18) des Halbleiterwafers (14) selektiv bis zum Freilegen wenigstens der im Bodenbereich (24) befindlichen Oxidschicht (26) rückgeätzt. Anschliessend wird die freigelegte Oxidschicht (26) bis wenigstens zu deren Durchtrennung angeätzt. Weiterhin sind auch eine insbesondere nach diesem Verfahren hergestellte Apertur (10) in einem Halbleitermaterial (12) sowie verschiedene Verwendungen einer solchen Apertur (10) beschrieben.

Abstract translation: 本发明涉及一种用于在半导体材料内孔（10）（12）的制造包括以下步骤：准备一个半导体晶片（14），例如，具有上表面（100）取向的硅晶片（16 ）和下表面（18）; 通过部分地蚀刻所述上表面（16），由此所述腔（20）包括一封闭的底部区域（24制造具有在所述半导体晶片（14）的上表面（16）的侧壁（22）的空腔（20） ）面向下表面（18）和其优选地具有，尤其是凸形或，特别地，凹角或边缘或这种类型的曲率。 氧化物层（26）上的半导体材料（12）至少在所述空腔（20）的区域中由半导体材料（12），氧化沉积后由此氧化物层（26）优选的不均匀性包括：（28） 的底部区域（24），半导体材料（14）被选择性地蚀刻背面的半导体晶片（14）的下表面（18）上，直到至少位于所述底部区域中的氧化层（26）（24）被暴露 ， 然后，暴露的氧化层（26）进行蚀刻，直到它被至少切断。 此外，本发明涉及在半导体材料内孔（10）（12）的爱尤其产生雅丁到本发明的方法，和向寻求孔（10）的不同的用途。

公开(公告)号：WO98032163A1

公开(公告)日：1998-07-23

申请号：PCT/US1998/001296

申请日：1998-01-22

IPC: B81C1/00 ,  H01L21/00 ,  H01L21/306 ,  H01L21/3065 ,  H01L21/3213 ,  H01L21/302

CPC classification number: B81C1/00531 ,  B81C99/0025 ,  B81C2201/0132 ,  B81C2201/0138 ,  H01J2237/3344 ,  H01L21/30604 ,  H01L21/3065 ,  H01L21/32135 ,  H01L21/67069

Abstract: An apparatus and method for gas-phase bromine trifluoride (BrF3) silicon isotropic room temperature etching system for both bulk and surface micromachining. The gas-phase BrF3 can be applied in a pulse mode and in a continuous flow mode. The etching rate in pulse mode is dependent on gas concentration, reaction pressure, pulse duration, pattern opening area and effective surface area.

Abstract translation: 用于体相和表面微加工的气相溴化三氟化硼（BrF 3）硅各向同性室温蚀刻系统的装置和方法。 气相BrF3可以以脉冲模式和连续流动模式施加。 脉冲模式下的蚀刻速率取决于气体浓度，反应压力，脉冲持续时间，图案开口面积和有效表面积。

公开(公告)号：WO1994018697A1

公开(公告)日：1994-08-18

申请号：PCT/US1993011584

申请日：1993-12-03

Applicant: CORNELL RESEARCH FOUNDATION, INC.

Inventor： CORNELL RESEARCH FOUNDATION, INC. ,  SHAW, Kevin, A. ,  ZHANG, Z., Lisa ,  MACDONALD, Noel, C.

IPC: H01L21/44

CPC classification number: B81C1/00619 ,  B81C1/00142 ,  B81C1/0015 ,  B81C1/00626 ,  B81C2201/0112 ,  B81C2201/0132 ,  B81C2201/053 ,  G01P15/0802 ,  G01P15/125 ,  G01P2015/0814 ,  G01P2015/0817 ,  G01P2015/0828 ,  Y10S73/01 ,  Y10S148/05

Abstract: The invention provides a single mask, low temperature reactive ion etching process for fabricating high aspect ratio, released single crystal microelectromechanical structures independent of crystal orientation. A dielectric mask (12) on a single-crystal substrate (154) is patterned to define isolating trenches. A protective conformal layer (28) is applied to the resultant structure. The conformal layer (28) on the floor of the trenches is removed and a second etch deepens the trench to expose the mesa walls which are removed during the release step by isotropic etching. A metal layer (44) is formed on the resultant structure providing opposed plates (156) and (158) of a capacitor. The cantilever beam (52) with the supporting end wall (152) extends the grid-like structure (150) into the protection of the deepened isolation trenches (54). A membrane can be added to the released structures to increase their weight for use in accelerometers, and polished for use as movable mirrors.

Abstract translation: 本发明提供单独的掩模，低温反应离子蚀刻工艺，用于制造高纵横比，独立于晶体取向的释放的单晶微机电结构。 将单晶衬底（154）上的介电掩模（12）图案化以限定隔离沟槽。 将保护性保形层（28）施加到所得结构。 去除沟槽底板上的共形层（28），并且第二蚀刻加深沟槽以暴露在释放步骤期间通过各向同性蚀刻去除的台面壁。 在所得结构上形成金属层（44），从而提供电容器的相对的板（156）和（158）。 具有支撑端壁（152）的悬臂梁（52）将格栅状结构（150）延伸到加深的隔离沟槽（54）的保护中。 可以向释放的结构添加膜以增加其用于加速度计的重量，并抛光用作可动反射镜。

公开(公告)号：EP3094112B1

公开(公告)日：2019-04-10

申请号：EP15738235.9

申请日：2015-04-23

Applicant: Microlink Senstech Shanghai Ltd.

Inventor： MIAO, Jianmin

IPC: H04R31/00 ,  H04R19/04 ,  H04R19/00

CPC classification number: B81C1/00158 ,  B81B3/0021 ,  B81B2201/0257 ,  B81B2203/0127 ,  B81C2201/0132 ,  B81C2203/038 ,  H04R19/005 ,  H04R19/04 ,  H04R31/003 ,  H04R2201/003

Abstract: This invention relates to the field of silicon microphone technology, more specifically, to a method for fabricating a MEMS microphone using multi-cavity SOI wafer by Si-Si fusion bonding technology, which comprises a multi-cavity silicon backplate (1) and a monocrystalline silicon diaphragm (2), both are separated with a layer of silicon dioxide (9) to form the capacitor of the MEMS microphone. The monocrystalline silicon diaphragm (2) has advantages such as low residual stress and good uniformity, which increase the yield and sensitivity of MEMS silicon microphone; the diaphragm comprises tiny release-assistant holes, spring structures with anchors and bumps, which can quickly release the residual stress and reduce the probability of stiction between the backplate (1) and the silicon diaphragm (2). This structure will further improve yield and reliability of MEMS microphone. Therefore, this invention provides simple and reliable process for fabricating MEMS microphones with high sensitivity, good uniformity, excellent reliability and high yield.

公开(公告)号：EP1113980B1

公开(公告)日：2018-11-07

申请号：EP99950524.1

申请日：1999-09-10

Applicant: WITec Wissenschaftliche Instrumente und Technologie GmbH

Inventor： KASSING, Rainer ,  MIHALCEA, Christophe ,  OESTERSCHULZE, Egbert

IPC: B81C1/00 ,  G01Q60/06 ,  G01Q60/22 ,  G01Q60/38

CPC classification number: B81C1/00087 ,  B81B2201/047 ,  B81B2203/0361 ,  B81C2201/0132 ,  G01Q60/06 ,  G01Q60/22 ,  G01Q60/38 ,  G02B27/58 ,  H01J9/02 ,  H01J37/09

公开(公告)号：EP3299787A1

公开(公告)日：2018-03-28

申请号：EP17181988.1

申请日：2017-07-18

Applicant: NXP USA, Inc.

Inventor： LIU, Lianjun ,  BOSE, Amitava

IPC: G01L9/00 ,  B81C1/00

CPC classification number: B81B3/0027 ,  B81B2201/0264 ,  B81B2207/015 ,  B81B2207/07 ,  B81C1/00246 ,  B81C2201/0132 ,  B81C2201/053 ,  B81C2203/0714 ,  B81C2203/075 ,  G01L9/0042 ,  G01L9/0045 ,  G01L9/0052 ,  G01L9/0054

Abstract: A device comprises a silicon-on-insulator (SOI) substrate having first and second silicon layers with an insulator layer interposed between them. A structural layer, having a first conductivity type, is formed on the first silicon layer. A well region, having a second conductivity type opposite from the first conductivity type, is formed in the structural layer, and resistors are diffused in the well region. A metallization structure is formed over the well region and the resistors. A first cavity extends through the metallization structure overlying the well region and a second cavity extends through the second silicon layer, with the second cavity stopping at one of the first silicon layer and the insulator layer. The well region interposed between the first and second cavities defines a diaphragm of a pressure sensor. An integrated circuit and the pressure sensor can be fabricated concurrently on the SOI substrate using a CMOS fabrication process.

Abstract translation: 一种器件包括具有第一和第二硅层的绝缘体上硅（SOI）衬底，绝缘体层插入它们之间。 具有第一导电类型的结构层形成在第一硅层上。 具有与第一导电类型相反的第二导电类型的阱区域形成在结构层中，并且电阻器在阱区域中扩散。 在阱区和电阻器上形成金属化结构。 第一腔体延伸穿过覆盖阱区域的金属化结构，并且第二腔体延伸穿过第二硅层，第二腔体在第一硅层和绝缘体层中的一个处停止。 介于第一腔和第二腔之间的井区域限定压力传感器的隔膜。 可以使用CMOS制造工艺在SOI衬底上同时制造集成电路和压力传感器。

公开(公告)号：EP3268304A1

公开(公告)日：2018-01-17

申请号：EP16710114.6

申请日：2016-03-04

Applicant: Endress+Hauser GmbH+Co. KG

Inventor： TEIPEN, Rafael ,  LEMKE, Benjamin

IPC: B81B3/00 ,  G01L9/00

CPC classification number: B81B3/0072 ,  B81B2201/0264 ,  B81B2203/0127 ,  B81B2203/0315 ,  B81B2203/04 ,  B81C1/00531 ,  B81C2201/0132 ,  G01L9/0048 ,  G01L9/0073 ,  G01L13/025 ,  G01L19/0618

Abstract: The invention relates to a MEMS sensor for metrologically sensing a measurement variable having improved resistance to overloading, which MEMS sensor comprises a plurality of layers (1, 3, 5), in particular silicon layers, arranged one on the other, the layers (1, 3, 5) of which MEMS sensor comprise at least one inner layer (5), which is arranged between a first layer (1) and a second layer (3), and in the inner layer (5) of which MEMS sensor at least one cut-out (7) extending through the inner layer (5) perpendicularly to the plane of the inner layer (5) is provided, which cut-out is adjoined on the outside at least in some segments by a region of the inner layer (5) forming a connecting element (9), which region is connected to the first layer (1) and the second layer (3), the MEMS sensor being distinguished in that a lateral surface (11) of the connecting element (9) bounding the cut-out (7) on the outside at least in some segments has, in an end region facing the first layer (1), a rounded shape that reduces the cross-sectional area of the cut-out (7) in the direction of the first layer (1) and, in an end region facing the second layer (3), a rounded shape that reduces the cross-sectional area of the cut-out (7) in the direction of the second layer (3).

公开(公告)号：EP3134916A4

公开(公告)日：2017-12-13

申请号：EP15782575

申请日：2015-04-22

Applicant: MASTER DYNAMIC LTD

Inventor： WANG YINGNAN ,  HUANG JIANXING

IPC: H01L21/308 ,  B81C1/00

CPC classification number: B28D5/04 ,  B81C1/00626 ,  B81C2201/0132 ,  C09K13/08 ,  G03F7/405

Abstract: A method of forming a multi-level component includes the step of forming at least one arrangement of micro trenches in a predetermined arrangement in a mask material by a lithography process. Another step involves applying one or more etching processes to a surface of a component upon which the mask is applied. The micro trenches have either first or second different aspect ratios. In the applying step, the component is etched by an aspect ratio dependent etch (ARDE) process so as to form an arrangement of micro trenches and micro pillars between adjacent micro trenches. Another step involves removing the arrangement of micro pillars from the component by a removal process. There is also a multi-level component made according to the above method with a first portion at a first level and a further portion of a further level different from the first level.