Abstract:
PURPOSE: The non-volatile memory device and manufacturing method thereof of the vertical folding structure arrange the NAND string to the folding structure. Height is controlled appropriately even when having the vertical structure. CONSTITUTION: In order to have the folding structure of being extended on the substrate(105) perpendicularity the semiconductor structure(130a) is offered. The semiconductor structure comprises the bottom part(31), and the first sidewall part(32) and the second sidewall part(33). The buried insulating layer(132) fills the space between second side walls and the first. A plurality of control gate electrodes is separately placed according to the first and second sidewall parts.
Abstract:
PURPOSE: A nonvolatile memory device and a manufacturing method thereof are provided to improve the integration of the nonvolatile memory device by simplifying the arrangement of a via plug and a word line. CONSTITUTION: A plurality of semiconductor pillars is formed on a substrate(105). A plurality of control gate electrodes(120) is stacked on the substrate to surround the semiconductor pillar. A plurality of dummy electrodes(125) is adjacently separated from the control gate electrode. A plurality of via plugs(170) is combined with the control gate electrode. A word line(180) is formed on the via plug. The via plug penetrates through one control gate electrode and a part of the dummy electrodes.
Abstract:
본 발명은 비터비 검출 장치에 관한 것으로서, 보다 상세하게는 광디스크용 비터비 검출장치에서 발생하는 코드 오류 경로가 제거된 비터비 검출 장치 및 방법에 관한 것이다. 본 발명에 의하면, 고속 동작이 가능하도록 radix를 확장함에 있어서, PR(a,b) 조건에서도 코드조건에 따라 1T 코드가 포함된 경로가 제거될 수 있는 비터비 검출 장치가 제공된다.
Abstract:
PURPOSE: A mirror for light scanning unit and method of manufacturing the same are provided to reduce the fabrication time by reducing the thickness of the protective layer. CONSTITUTION: The mirror for the optical scanning apparatus comprises the epoxy(210), the silver layer(220), and the protective layer(230) and MgO layer(225). The silver layer is formed in epoxy. The protective layer is formed on the top of the silver layer. The MgO layer is formed between the silver layer and protective layer. The bonding layer(212) is formed between epoxy and silver layer. The bonding layer is formed in order to increase the adhesive force between epoxy and the silver layer. The bonding layer is formed on the top of epoxy with the sputtering method by evaporating Ti to the prescribed thickness. The thickness of bonding layer is approximately 50~100Å. The MgO layer increases the adhesive force between the protective layer and the silver layer.
Abstract:
A resistivity memory device is provided to prevent or minimize out diffusion in which chemical species is diffused to the outside of a resistance alteration layer by using a diffusion stop layer. A resistivity memory device comprises a switching element and a storage node(S2) connected to the switching element. The storage node comprises a first electrode(40), a resistance alteration layer(50) and a second electrode(60) which are successively laminated. A diffusion stop layer is equipped between the first electrode and the resistance alteration layer or the resistance alteration layer and the second electrode. Binding energy of the diffusion stop layer is greater than binding energy of the resistance alteration layer. The resistance alteration layer is a transition metal oxide layer. The diffusion stop layer is a nitride layer. The transition metal oxide layer is one among a nickel oxide layer, a titanium oxide layer, a zirconium oxide layer, a zinc oxide layer and a copper oxide layer.
Abstract:
소정 거리만큼 이격된 소오스 및 드레인 영역이 형성된 반도체 기판; 및 상기 소오스 및 드레인 영역사이의 상기 반도체 기판 상에 양단이 상기 소오스 및 드레인 영역과 접촉되도록 형성된 게이트 적층물을 구비하는 비휘발성 반도체 메모리 장치에 있어서, 상기 게이트 적층물은 터널링막, 질화막(Si 3 N 4 )보다 유전율이 크고 제1 불순물이 도핑된 제1 트랩 물질막, 상기 질화막보다 유전율이 큰 제1 절연막 및 게이트 전극이 순차적으로 적층되어 구성되고, 상기 제1 불순물은 Dy를 포함하는 란탄계열원소인 것을 특징으로 하는 비휘발성 반도체 메모리 장치를 제공한다. 이러한 본 발명을 이용하면, 도핑 농도에 따라 트랩밀도를 효과적으로 조절할 수 있고, 그에 따라 종래보다 낮은 전압으로 데이터를 기록 및 소거할 수 있으며, 종래보다 빠른 동작 속도를 얻을 수 있다.
Abstract:
The field effect transistor and a manufacturing method thereof are provided to increase the driving speed and decrease the driving voltage by equipping the germanium nano-rods in which the mobility is bigger than the silicon as a channel. The field effect transistor(100) includes the gate oxide(130) formed on the substrate(110); germanium nano-rods(140) in which both ends are exposed; the source electrode(151) and the drain electrode(152) connected with the both ends of the germanium nano-rods; the gate electrode(160) formed on the gate oxide between the source electrode and drain electrode. The germanium nano-rods are embedded in the gate oxide.
Abstract:
A method and a node for generating a distributed RSA(Rivest Shamir Adleman) signature in an ad-hoc network are provided to share a distributed signature function safely by determining verification for key sharing information and a partial signature through a partial signature witness. A method for generating a distributed RSA signature in an ad-hoc network includes the steps of: at a dealer node, distributing key sharing information generated using an MDS(Maximum Distance Separable) code and a random symmetric matrix to a plurality of nodes(S301); at the nodes, generating a partial signature using the distributed key sharing information, and transmitting the partial signature to the signature generation node(S302); at the signature generation node, generating an RSA signature using the partial signature(S303). The RSA signature is generated using the partial signature received from a less number of nodes than the nodes.
Abstract:
An image processing apparatus and method for reducing power consumption without deteriorating image are provided to analyze image information by using a histogram, and change the luminance of an image and adjust the saturation of the image by using an image class in the location information on a frame of a pixel determined according to the analyzed result, thereby reducing the power consumption without the deterioration of the image. A histogram generator(101) generates a luminance histogram indicating the luminance distribution of an input image. A class determiner(102) determines one of plural classes on the basis of the generated luminance histogram. A luminance converter(103) increases the luminance of the input image in correspondence to the determined class. A power converter(104) sets the size of the driving power of an image processing apparatus at a low level in inverse proportion to an increase of the luminance.
Abstract:
A sparse w-NAF key generating method, a processing method, an encrypting method using the same are provided to increase an encrypting speed by decreasing a scalar multiplication quantity and an exponential manipulation quantity. An encryption apparatus includes a key generator(100), an exponential calculator(200), and an encryption unit(300). The key generator generates an unsigned-w-NAF(Non-Adjacent Form) key. The w-NAF key is an odd number whose absolute value of a non-zero coefficient is smaller than 2^(w-1). A maximum number of non-zero coefficients of w consecutive coefficients is one. The exponential calculator performs an exponential manipulation by using the non-signed w-NAF key as an exponent. The encryption unit performs an encryption process on the exponential result from the exponential calculator.