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    ОБЛАСТЬ УПРАВЛЕНИЯ ДЛЯ АДМИНИСТРИРОВАНИЯ МНОЖЕСТВЕННЫМИ ПОТОКАМИ В КОМПЬЮТЕРЕ
    181.
    发明专利
    ОБЛАСТЬ УПРАВЛЕНИЯ ДЛЯ АДМИНИСТРИРОВАНИЯ МНОЖЕСТВЕННЫМИ ПОТОКАМИ В КОМПЬЮТЕРЕ 未知

    公开(公告)号：RU2662695C2

    公开(公告)日：2018-07-26

    申请号：RU2016127442

    申请日：2015-03-16

    Applicant: IBM

    Inventor： KHELLER LAJZA KRANTON ,  BREDBERI DZHONATAN DEJVID ,  KUBALA DZHEFFRI POL ,  FARRELL MARK ,  OSISEK DEJMIAN LEO ,  GREJNER DEN ,  SLEGEL TIMOTI ,  BUSABA FADI YUSUF ,  SHMIDT DONALD UILLYAM

    IPC: G06F9/455 ,  G06F9/50

    Abstract: Изобретениеотноситсяк администрированиюмножественнымипотокамив компьютере. Техническийрезультатзаключаетсяв сокращениииздержекпокоординацииресурсовмеждурабочимипотокамигипервизорав многопоточномокружении. Компьютернаясистемасодержитконфигурациювиртуальноймашины (VM), содержащуюодноилинесколькоядер. Каждоеядроспособнок работев режимеединственногопотока (ST) илив многопоточном (МТ) режиме. Режим ST состоитизединственногопотока, арежимМТсостоитизнесколькихпотоковнасовместноиспользуемыхресурсахсоответствующегоядра. Компьютернаясистемавключаетв себяориентированнуюнаядрообласть (COSCA) управлениясистемы, содержащуюобщуюобласть, представляющуювсеизчислаодногоилинесколькихядерконфигурации VM, иотдельныеобластиописанияядрадлякаждогоядраизчислаодногоилинесколькихядерв конфигурации VM. Каждаяобластьописанияядрауказываетнаместоположениеоднойилинесколькихобластейописанияпотока, каждаяизкоторыхпредставляетпотокв соответствующемядре, икаждаяобластьописанияпотокауказываетнаместоположениеописаниясостояниясоответствующегопотока. 3 н. и 17 з.п. ф-лы, 14 ил.

    Dynamic enablement of multithreading
    182.
    发明专利
    Dynamic enablement of multithreading 未知

    公开(公告)号：AU2015238632B2

    公开(公告)日：2018-04-26

    申请号：AU2015238632

    申请日：2015-03-19

    Applicant: IBM

    Inventor： GREINER DAN ,  FARRELL MARK ,  OSISEK DAMIAN LEO ,  SCHMIDT DONALD WILLIAM ,  BUSABA FADI YUSUF ,  KUBALA JEFFREY PAUL ,  BRADBURY JONATHAN DAVID ,  HELLER LISA CRANTON ,  SLEGEL TIMOTHY ,  GAINEY JR CHARLES ,  JACOBI CHRISTIAN

    IPC: G06F9/50 ,  G06F9/38

    Abstract: Embodiments relate to dynamic enablement of multithreading. According to an aspect, a computer system includes a configuration with a core configurable between a single thread (ST) mode and a multithreading (MT) mode. The ST mode addresses a primary thread, and the MT mode addresses the primary thread and one or more secondary threads on shared resources of the core. The computer system also includes a multithreading facility configured to control the configuration to perform a method. The method includes executing in the primary thread in the ST mode, an MT mode setting instruction. A number of threads requested is obtained from a location specified by the MT mode setting instruction. Based on determining that the number of threads requested indicates multiple threads, the MT mode is enabled to execute the multiple threads including the primary thread and the one or more secondary threads.

    STORE/STORE BLOCK INSTRUCTIONS FOR COMMUNICATING WITH ADAPTERS
    185.
    发明专利
    STORE/STORE BLOCK INSTRUCTIONS FOR COMMUNICATING WITH ADAPTERS 未知

    公开(公告)号：CA2800631C

    公开(公告)日：2018-02-13

    申请号：CA2800631

    申请日：2010-11-08

    Applicant: IBM

    Inventor： GREINER DAN ,  CRADDOCK DAVID ,  GREGG THOMAS ,  FARRELL MARK

    IPC: G06F9/312 ,  G06F13/38

    Abstract: Communication with adapters of a computing environment is facilitated. Control instructions specifically designed for communicating data to and from the adapters are provided to facilitate the communication. The instructions explicitly target the adapters. Information provided in an instruction is used to steer the instruction to an appropriate location within the adapter, such as a Peripheral Component Interconnect (PCI) adapter or a Peripheral Component Interconnect Express (PCIe) adapter.

    CONTROLLING EXECUTION OF THREADS IN A MULTI-THREADED PROCESSOR
    187.
    发明专利
    CONTROLLING EXECUTION OF THREADS IN A MULTI-THREADED PROCESSOR 未知

    公开(公告)号：SG11201701612VA

    公开(公告)日：2017-03-30

    申请号：SG11201701612V

    申请日：2015-10-21

    Applicant: IBM

    Inventor： SLEGEL TIMOTHY ,  ALEXANDER KHARY JASON ,  BUSABA FADI YUSUF ,  FARRELL MARK ,  RELL JR JOHN GILBERT

    IPC: G06F9/30

    Abstract: Execution of threads in a processor core is controlled. The processor core supports simultaneous multi-threading (SMT) such that there can be effectively multiple logical central processing units (CPUs) operating simultaneously on the same physical processor hardware. Each of these logical CPUs is considered a thread. In such a multi-threading environment, it may be desirous for one thread to stop other threads on the processor core from executing. This may be in response to running a critical sequence or other sequence that needs the processor core resources or is manipulating processor core resources in a way that other threads would interfere with its execution.

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