公开(公告)号：EP2054338B1

公开(公告)日：2009-11-11

申请号：EP07727715.0

申请日：2007-04-03

Applicant: COMMISSARIAT A L'ENERGIE ATOMIQUE

Inventor： CHARLET, Barbara ,  LE POCHE, Hélène ,  GOBIL, Yveline

IPC: B81C1/00

CPC classification number: B81C1/00833 ,  B81B2203/0315 ,  B81C2201/019 ,  B81C2201/053 ,  H01J9/025

Abstract: The invention relates to a method of protecting the interior of at least one cavity (4) which has a part of interest (5) and which opens onto a face of a microstructured element (1), the method consisting in depositing onto said face a non-conformal layer (6) of a protective material, said non-conformal layer plugging the cavity without covering the part of interest. The invention also relates to a method of producing a device comprising such a microstructured element.

Abstract translation: 本发明涉及一种保护至少一个空腔（4）的内部的方法，所述至少一个空腔（4）具有感兴趣的部分（5）并且通向微结构元件（1）的面上，所述方法包括在所述面上沉积 非保形材料层（6），所述非保形层在没有覆盖感兴趣部分的情况下堵塞腔体。 本发明还涉及制造包含这种微结构元件的器件的方法。

公开(公告)号：EP2075222A1

公开(公告)日：2009-07-01

申请号：EP08172514.5

申请日：2008-12-22

Applicant: Commissariat à l'Energie Atomique

Inventor： Robert, Philippe ,  Nguyen, Valérie

IPC: B81C1/00

CPC classification number: B81C1/00484 ,  B81C1/00682 ,  B81C2201/053

Abstract: L'invention concerne un procédé de fabrication d'au moins un composant mécanique d'une structure MEMS ou NEMS à partir d'un substrat de silicium monocristallin, comprenant les étapes de :
- formation de zones d'ancrage dans une face du substrat pour délimiter le composant mécanique,
- formation, sur la face du substrat, d'une couche de protection inférieure en matériau autre que le silicium et obtenue par épitaxie à partir de la face du substrat,
- formation sur la couche de protection inférieure d'une couche de silicium obtenue par épitaxie à partir de la couche de protection inférieure,
- formation d'une couche de protection supérieure sur la couche de silicium,
- gravure de la couche de protection supérieure, de la couche de silicium et de la couche de protection inférieure, selon un motif de définition du composant mécanique, jusqu'à atteindre le substrat et fournir des voies d'accès au substrat,
- formation d'une couche de protection sur les parois formées par la gravure du motif du composant mécanique dans la couche de silicium épitaxiée,
- libération du composant mécanique par gravure isotrope du substrat à partir des voies d'accès au substrat, cette gravure isotrope n'attaquant pas les couches de protection inférieure et supérieure et la couche de protection des parois.

Abstract translation: 该方法包括在硅层（7）上形成上保护层（9），并且在锚固区（4）之间蚀刻下保护层（5）和层（9,7），直到获得单晶硅衬底 （1），并且在所述衬底处建立存取路径（10）。 保护层（11）形成在通过蚀刻外延硅层中的机械部件的限定图案形成的壁上。 该组件通过各向同性蚀刻从基板的各向同性蚀刻而从访问路径释放，其中各向同性蚀刻不侵蚀层（5,9,11）。

公开(公告)号：EP1842224A1

公开(公告)日：2007-10-10

申请号：EP05854003.0

申请日：2005-12-14

Applicant: Freescale Semiconductor, Inc.

Inventor： MCDONALD, William G. ,  HOOPER, Stephen R. ,  SALIAN, Arvind S.

IPC: H01L21/00

CPC classification number: B81C1/00309 ,  B81C2201/053

Abstract: Methods are provided for manufacturing a sensor (100). The method comprises depositing a sacrificial material (330) at a first predetermined thickness onto a wafer having at least one sense element mounted thereon, the sacrificial material deposited at least partially onto the at least one sense element, forming an encapsulating layer (332) at a second predetermined thickness less than the first predetermined thickness over the wafer and around the deposited sacrificial material, and removing the sacrificial material. Apparatus for a sensor manufactured by the aforementioned method are also provided.

公开(公告)号：EP1161985B1

公开(公告)日：2005-10-26

申请号：EP00830400.8

申请日：2000-06-05

Applicant: STMicroelectronics S.r.l.

Inventor： Villa, Flavio ,  Mastromatteo, Ubaldo ,  Barlocchi, Gabriele ,  Cattaneo, Mauro

IPC: B01J19/00

CPC classification number: B81C1/00119 ,  B01J19/0093 ,  B01L3/5027 ,  B01L3/502707 ,  B01L7/52 ,  B01L7/525 ,  B01L2200/12 ,  B01L2300/0645 ,  B01L2300/1827 ,  B01L2300/185 ,  B01L2300/1883 ,  B81B2201/0214 ,  B81B2201/051 ,  B81B2203/0315 ,  B81B2203/0338 ,  B81C2201/053

公开(公告)号：EP1403211A3

公开(公告)日：2005-09-14

申请号：EP03255693.8

申请日：2003-09-11

Applicant: PTS Corporation

Inventor： Staple, Bevan ,  Buriak, Jilian

IPC: B81B3/00 ,  B81C1/00

CPC classification number: B82Y30/00 ,  B81C1/00476 ,  B81C1/00801 ,  B81C2201/0114 ,  B81C2201/0133 ,  B81C2201/0139 ,  B81C2201/053

Abstract: A microelectromechanical structure is formed by depositing sacrificial and structural material over a substrate to form a structural layer on a component electrically attached with the substrate (step 102). The galvanic potential of the structural layer is greater than the galvanic potential of the component. At least a portion of the structural material is covered with a protective material that has a galvanic potential less than or equal to the galvanic potential of the component (step 104 or 106). The sacrificial material is removed with a release solution (step 108 or 110). At least one of the protective material and release solution is surfactanated, the surfactant functionalizing a surface of the component.

公开(公告)号：EP1227061A3

公开(公告)日：2004-03-03

申请号：EP01127971.8

申请日：2001-11-24

Applicant: ROBERT BOSCH GMBH

Inventor： Fischer, Frank ,  Bischof, Udo ,  Metzger, Lars

IPC: B81B3/00 ,  B81C1/00

CPC classification number: B81C1/00896 ,  B81C2201/053

Abstract: Die Erfindung schafft ein Verfahren zum Herstellen eines mikromechanischen Bauelements mit den Schritten: Bereitstellen eines Substrats (1; 2; 4) mit einer Vorderseite und einer Rückseite; Strukturieren der Vorderseite des Substrats (1; 2; 4); zumindest teilweises Abdecken der strukturierten Vorderseite des Substrats (1; 2; 4) mit einer Germanium-enthaltenden Schutzschicht (7; 7'; 7"); Strukturieren der Rückseite des Substrats (1; 2; 4); und zumindest teilweises Entfernen der Germanium-enthaltenden Schutzschicht (7; 7'; 7") von der strukturierten Vorderseite des Substrats (1; 2; 4).

公开(公告)号：EP1377517A1

公开(公告)日：2004-01-07

申请号：EP02719681.5

申请日：2002-03-27

Applicant: Danish Electronics Light & Acoustics (Delta)

Inventor： LISBY, Torben ,  BRANEBJERG, Jens, A.

IPC: B81B3/00 ,  B81B7/00 ,  G02B6/42 ,  B01L3/00

CPC classification number: G02B6/4226 ,  B01L3/502707 ,  B01L2200/12 ,  B01L2300/123 ,  B81C1/0019 ,  B81C2201/017 ,  B81C2201/053 ,  B81C2203/0136 ,  G02B6/3502 ,  G02B6/3584

Abstract: A method for producing a unitary flexible microelement from a supporting wafer is provided. The unitary flexible microelement defines a supporting body having a solid region and a flexible region consisting of a thin part of the supporting wafer. The method comprises the following steps: defining thickness of the flexible region and growing an upper insulating layer to the upper surface covering the predefined area and growing a lower insulating layer to the lower surface covering the solid region. The method comprises defining a conductive layer on the predefined area of the upper surface, depositing a final insulating layer on the upper surface covering the conductive layer and depositing a metallic protective layer on the upper surface covering the insulating layer. Furthermore, the method comprises etching the lower surface until the etching reaches the thickness of the flexible region, and deepositing a conductive layer on the lower surface to establish a coaxial conductor.

公开(公告)号：EP0983609B1

公开(公告)日：2002-01-02

申请号：EP98925745.6

申请日：1998-05-19

Applicant: THALES AVIONICS S.A.

Inventor： LEFORT, Olivier Thomson-CSF Protection & Conseil ,  THOMAS, Isabelle Thomson-CSF Protection & Conseil

IPC: H01L21/00 ,  G01P15/08

CPC classification number: B81C1/0015 ,  B81B2201/0235 ,  B81C2201/053 ,  G01P15/0802 ,  G01P15/125

Abstract: The invention concerns the production of machined silicon micro-sensors, in particular accelerometers for assistance to navigation in aircraft, and pressure sensors. In order to improve the production of certain active parts of the sensor, and particularly of a beam (32) forming a resonator, whereof the width and thickness characteristics should be well controlled, the method consists in: producing, by micro-machining the silicon on a first plate (30), a beam with thickness equal to the required final thickness, said beam being coated on its top surface with a mask defining the required final width; assembling the plate (30) with another (10); oxidising the two surfaces of the beam to coat them with a thin protective layer; removing, by vertical directional etching, said thin protective layer on the top surface without removing the mask already there; working on the silicon in the zone exposed by the previous operation, using vertical directional etching on the top surface, until all the part of the beam not protected by the mask is eliminated thereby producing the beam with the required width.

公开(公告)号：EP0922944A2

公开(公告)日：1999-06-16

申请号：EP98830266.7

申请日：1998-04-30

Applicant: STMicroelectronics S.r.l.

Inventor： Montanini, Pietro ,  Ferrera, Marco ,  Castoldi, Laura ,  Gelmi, Ilaria

IPC: G01L9/00

CPC classification number: B81C1/00476 ,  B81B2203/033 ,  B81C1/00801 ,  B81C2201/0177 ,  B81C2201/053 ,  G01C19/56 ,  G01P15/0802 ,  G01P15/097 ,  G01P15/125 ,  H01L21/76202 ,  H01L21/764

Abstract: The method is based on the use of a silicon carbide mask for removing a sacrificial region. In case of manufacture of integrated semiconductor material structures, the following steps are performed: forming a sacrificial region (6) of silicon oxide on a substrate (1) of semiconductor material; growing a pseudo-epitaxial layer (8); forming an electronic circuit (10-13, 18); depositing a silicon carbide layer (21); defining photolithographycally the silicon carbon layer so as to form an etching mask (23) containing the topography of a microstructure (27) to be formed; with the etching mask (23), forming trenches (25) in the pseudo-epitaxial layer (8) as far as the sacrificial region (6) so as to laterally define the microstructure; and removing the sacrificial region (6) through the trenches (25).

Abstract translation: 该方法基于使用碳化硅掩模去除牺牲区域。 在制造集成半导体材料结构的情况下，执行以下步骤：在半导体材料的衬底（1）上形成氧化硅的牺牲区域（6） 生长伪外延层（8）; 形成电子电路（10-13,18）; 沉积碳化硅层（21）; 定义光刻硅碳层以形成包含待形成的微结构（27）的形貌的蚀刻掩模（23） 利用蚀刻掩模（23），在伪外延层（8）中形成直至牺牲区域（6）的沟槽（25）以横向地限定微结构; 并通过沟槽（25）去除牺牲区域（6）。

公开(公告)号：EP0567075A2

公开(公告)日：1993-10-27

申请号：EP93106391.1

申请日：1993-04-20

Applicant: NIPPONDENSO CO., LTD.

Inventor： Fukada, Tsuyoshi ,  Yoshino, Yoshimi ,  Tanizawa, Yukihiko

IPC: H01L21/306 ,  H01L21/78 ,  H01L21/308

CPC classification number: B81C1/00888 ,  B81B2201/0235 ,  B81C1/00158 ,  B81C2201/0114 ,  B81C2201/053 ,  G01L9/0055 ,  G01P15/0802 ,  G01P15/123 ,  H01L21/3063 ,  H01L21/78 ,  Y10S148/028 ,  Y10S148/159 ,  Y10S438/977

Abstract: A method for producing a semiconductor device is capable of solving problems related to dicing a metal thin film used for electrochemical etching.
According to the method, an n type epitaxial thin layer (36) is formed on a p type single-crystal silicon wafer (35). An n + type diffusion layer (38) is formed in a scribe line area on the epitaxial layer (36). An n + type diffusion layer (39) is formed in an area of the epitaxial layer (36) which corresponds to the predetermined part of the wafter (35). Aluminum film (40, 41) is formed over the diffusion layers (38, 39), respectively. The aluminum film (40) has a clearance (65) for passing a dicing blade (66). Predetermined parts of the wafer (35) are electrochemically etched by supplying electricity through the aluminum film (40), the diffusion layers (38) and (39), to leave predetermined parts of the epitaxial layer (36). The wafer (35) is diced into chips along the scribe line area. Each of the chips forms the semiconductor device.
The electrochemical etching of the wafer (35) is carried out after the formation of the aluminum film (40, 41), by immersing the wafer (35) in a KOH aqueous solution (76) and by supplying electricity through the aluminum film (40). The electrochemical etching is terminated at an inflection point where an etching current inflects to a constant level from a peak level.
During the electrochemical etching, the diffusion layer (39) reduces horizontal resistance in the epitaxial layer (36), so that the etched parts receive a sufficient potential to perform the etching.

Abstract translation: 半导体器件的制造方法能够解决与用于电化学蚀刻的金属薄膜切割相关的问题。 根据该方法，在p型单晶硅晶片（35）上形成n型外延薄层（36）。 在外延层（36）上的划线区域中形成n +型扩散层（38）。 在外延层（36）的对应于浮体（35）的预定部分的区域中形成n +型扩散层（39）。 铝膜（40,41）分别形成在扩散层（38,39）上。 铝膜（40）具有用于通过切割刀片（66）的间隙（65）。 通过供电通过铝膜（40），扩散层（38）和（39）来电蚀刻晶片（35）的预定部分，以留下外延层（36）的预定部分。 将晶片（35）沿着划线区切成芯片。 每个芯片形成半导体器件。 通过将晶片（35）浸渍在KOH水溶液（76）中并通过铝膜（40）供电，在形成铝膜（40,41）之后进行晶片（35）的电化学蚀刻 ）。 在蚀刻电流从峰值水平变为恒定水平的拐点处终止电化学蚀刻。 在电化学蚀刻期间，扩散层（39）减小了外延层（36）中的水平电阻，使得蚀刻部分具有足够的电位来进行蚀刻。