公开(公告)号：JPH0799206A

公开(公告)日：1995-04-11

申请号：JP12518694

申请日：1994-06-07

Applicant: CONS RIC MICROELETTRONICA

Inventor： SEBASUCHIAANO APARO ,  ARUFUONSO PATEI ,  ARUDO BITANTSUA

IPC: H01L27/06 ,  H01L27/07 ,  H01L21/331 ,  H01L21/06 ,  H01L29/73

Abstract: PURPOSE: To remove a problem of parasitic elements by a method wherein a first junction diode is connected between an external base terminal and a collector of a bipolar switching transistor, and a second junction diode is connected between the external base terminal and a base area of the bipolar switching transistor. CONSTITUTION: A first junction diode D1 comprising a base-collector junction of zero gain transistors is connected between an external base terminal B2 and a collector 2 of a bipolar switching transistor T. Meanwhile, a second junction diode D2 comprising a base-emitter junction of zero gain transistors is connected between the external base terminal B2 and a base area P2 of the bipolar switching transistor T. Thereby, the transistors can be manufactured without causing a problem in a parasitic element.

公开(公告)号：JPH06350425A

公开(公告)日：1994-12-22

申请号：JP9588294

申请日：1994-04-09

Applicant: ST MICROELECTRONICS SRL ,  CONS RIC MICROELETTRONICA

Inventor： BONTEMPO GREGORIO ,  MILAZZO PATRIZIA ,  ALZATI ANGELO

IPC: H03K17/04 ,  H03K17/0412 ,  H03K17/16 ,  H03K17/687

Abstract: PURPOSE: To provide a control circuit substantially equalizing the delay of the turn-on and turn-off of an output signal by reducing the delay of switching. CONSTITUTION: The control circuit includes a first current oscillator I1 charging the driving node of a power transistor and a second current oscillator I2 discharging a driving node and is provided with a third current oscillator I3 for discharging a node. Discharge by the third current oscillator is controlled by a signal to adjust a turn-off delay time and a turn-on delay time.

公开(公告)号：JPH06350031A

公开(公告)日：1994-12-22

申请号：JP9999794

申请日：1994-05-13

Applicant: CONS RIC MICROELETTRONICA

Inventor： ZAMBRONO RAFFAELE

IPC: H01L27/04 ,  H01L21/822 ,  H01L27/02

Abstract: PURPOSE: To protect a power device from overvoltage by providing a second conductivity-type doped region with a semiconductor region having a suitable low concentration or medium concentration for forming a junction-type diode that has a sufficiently high breakdown voltage. CONSTITUTION: A plurality of junction-type diodes D1-D5 are provided by being connected in series. The diodes D1-D5 are provided with a first electrode, composed of a heavily-doped region 1 of a first conductivity type and a second electrode composed of a medium or lightly-doped region 2 of a second conductivity type. The second conductivity type medium-doped or lightly-doped region 2 sets, a sufficiently high breakdown voltage, namely, 5 V or more, is set. Thus, power devices, namely MOSFET and IGBT, can be effectively protected from overvoltage.

公开(公告)号：JPH06302826A

公开(公告)日：1994-10-28

申请号：JP32552092

申请日：1992-12-04

Applicant: CONS RIC MICROELETTRONICA

Inventor： RAFUAERE ZANBURAANO

IPC: H01L21/336 ,  H01L29/423 ,  H01L29/78 ,  H01L29/784

Abstract: PURPOSE: To reduce the possibility of the short-circuit between a gate and source regions of an IGFET. CONSTITUTION: An n-type Si layer 2 is epitaxially grown in a single crystal substrate, the surface is oxidized to form a field oxide film 4, ions are implanted in the Si layer and diffused to form a bulk region and source region and a gate polycrystalline Si layer 5 is laminated and selectively etched to form a gate electrode.

公开(公告)号：JPH05226597A

公开(公告)日：1993-09-03

申请号：JP31502492

申请日：1992-11-25

Applicant: ST MICROELECTRONICS SRL ,  CONS RIC MICROELETTRONICA

Inventor： PAPARO MARIO ,  AIELLO NATALE

IPC: H01L21/8238 ,  H01L21/761 ,  H01L27/088 ,  H01L27/092 ,  H01L29/78 ,  H02M7/219

Abstract: PURPOSE: To provide a large-current MOS transistor integrated bridge which is formed in a monolithic structure on a single Si substrate, optimizing a conduction power loss. CONSTITUTION: An N -type substrate 3, which includes at least two arms respectively comprised of first and second MOS Trs and which forms a positive potential output terminal K1, covered with an N -type epitaxial layer 4. A bridge is comprised of a P and P -type insulating regions 13, 25 and 14, 16, including N -type drain regions 15, 16, N-type drain regions 19, 20 and a pair of N -type source regions 23, 24 forming continuously P-type main body regions 21, 22 and a negative potential output terminal with respect to each of the first Tr. The bridge also consists of an N -type drain regions 5, 6, including N-type drain regions 31, 32 with respect to each of the second Tr, continuously P-type main body regions 9, 10 and a pair of N -type regions 11, 12 forming respectively corresponding ac inputs A3, A4.

公开(公告)号：JP2000112761A

公开(公告)日：2000-04-21

申请号：JP32747799

申请日：1999-11-17

Applicant: CONS RIC MICROELETTRONICA

Inventor： PAPPALARDO FRANCESCO ,  MATRANGA VINCENZO ,  TESI DAVIDE ,  DI BELLA DARIO

IPC: G06F9/44 ,  G06F7/48 ,  G06F7/499 ,  G06N7/02 ,  G06N7/04

Abstract: PROBLEM TO BE SOLVED: To provide a circuit for calculating the attribute degree of the antecedent part of a fuzzy rule determining the intersection of a membership function and an input by a simple and economical system. SOLUTION: A circuit for dividing a dividend by 2n through the use of round-up or round-down approximation includes a register 32 which includes a binary number to be devided and an adder 48 which is connected to the register 32, receives the (n+1) bit of the binary number to be divided to a highest- order bit by a first input A and the n-numbered bit of the binary number to be divided by a second input B, adds the first input A to a second input B and outputting a total value A+B. Then, the binary number divided by the total value A+B outputted by the adder 48 is the result of round-up and round- down approximation of the binary number divided by 2n.

公开(公告)号：JPH0964729A

公开(公告)日：1997-03-07

申请号：JP35098695

申请日：1995-12-25

Applicant: SGS THOMSON MICROELECTRONICS ,  CONS RIC MICROELETTRONICA

Inventor： MERUKIOORE BURUTSUKORERI ,  GAETANO KOSENTEINO ,  MARUKO DEMICHIERI ,  JIYUSETSUPE PATSUTEI

IPC: H03L7/093 ,  H03L7/089

Abstract: PROBLEM TO BE SOLVED: To obtain a highly precise differential charge pump circuit which can suppress a common mode error to a minimum and which can prevent the occurrence of common mode voltage fluctuation without a correction instruction. SOLUTION: Two same current sources Gb1 and Gb2 are connected to nodes A and B and they continuously inject current I to the nodes A and B. Two pairs of current sources Gc1 and Gc2 and Gc3 and Gc4, which are switch- controlled, are connected to the nodes A and B and they can pull in current I from the nodes to which the respective current sources are connected. The two current sources of the respective pairs of the current sources are controlled by one of a pair of control signals and the inverse signal of the other signal. Then, the whole two pairs of the current sources which are switch-controlled can be set to the same type (N type). Two current sources are set to the same type (P type) and they are controlled by a common mode feedback loop.

公开(公告)号：JPH08288826A

公开(公告)日：1996-11-01

申请号：JP7890596

申请日：1996-04-01

Applicant: CONS RIC MICROELETTRONICA

Inventor： FURANKO RENCHINI ,  JIYORUJIO KATANZARO

IPC: H03K19/00 ,  H03K19/003 ,  H03K19/0175 ,  H03K19/0948

Abstract: PROBLEM TO BE SOLVED: To provide a three-state CMOS output buffer which is made structurally different from a known circuit and conquer the fault of known circuit while being made appropriate for the purpose of use in an integrated circuit required to connect various voltage power sources. SOLUTION: A pull-up transistor M15 has an auxiliary circuit 9 for holding a switchable bulk line 2, which is connected to a voltage power source VDD while the voltage of output node 4 is not higher than the power supply voltage VDD, while having a bulk electrode connected to the switchable bulk line 2. Then, a 1st logic gate 3 is equipped with means M17, M11 and M12 for transmitting the voltage of output node 4 to the switchable bulk line 2 when the voltage of output node 4 exceeds the power supply voltage VDD.

公开(公告)号：JPH08288810A

公开(公告)日：1996-11-01

申请号：JP27290595

申请日：1995-10-20

Applicant: CONS RIC MICROELETTRONICA

Inventor： JIYOBUANNI GATSURI ,  JIYUZETSUPE SHITSURA

IPC: H01L27/04 ,  H01L21/822 ,  H01L27/06 ,  H03F1/52 ,  H03K17/08

Abstract: PROBLEM TO BE SOLVED: To provide a method and a circuit for preventing a latch-down phenomenon at a transistor protected from the runaway of its safe operating area(SOA). SOLUTION: By adding a 1st protection circuit PCI(for the runaway of SOA) having a 2nd protection circuit PC2 for driving the control terminal of transistor PT so as not to be affected by a load watched from the output terminal of transistor PT while keeping the value of current flowing through a main conduction path almost constant when that value tends to drop lower than a prescribed downside limit value because of 1st protection in the case of increasing a voltage loaded to the main conduction path of transistor PT, the transistor PT can always supply a correspondent current to the load up to an upside breakdown limit value, VMAX allowable for this transistor PT.

公开(公告)号：JPH08250599A

公开(公告)日：1996-09-27

申请号：JP3789496

申请日：1996-02-26

Applicant: CONS RIC MICROELETTRONICA

Inventor： NATAARE AIETSURO

IPC: H01L27/06 ,  H01L21/8222 ,  H01L27/02 ,  H03K19/003

Abstract: PROBLEM TO BE SOLVED: To positively perform reverse biasing of a parasitic diode that is formed between an epitaxial well and its adjacent region. SOLUTION: A first transistor T1 and a second transistor T2 that operates in reverse phase to the transistor T1 are provided, and the first transistor T1 is connected between a power supply and an epitaxial well, when the power supply voltage is positive. On the other hand, when the transistor T2 is cut off and the power supply voltage is negative, the second transistor T2 is connected between the epitaxial well and a ground potential GND for saturated state, thus retaining the epitaxial well at a ground voltage which is the highest voltage in a device.