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    CROSSING-CABLE DETECTING SYSTEM BETWEEN SECTIONS
    11.
    发明专利
    CROSSING-CABLE DETECTING SYSTEM BETWEEN SECTIONS 失效

    公开(公告)号：JPH07146826A

    公开(公告)日：1995-06-06

    申请号：JP15098294

    申请日：1994-07-01

    Applicant: TANDEM COMPUTERS INC

    Inventor： MAAKU EI TEIRAA

    IPC: G06F3/00 ,  G01R31/04 ,  G06F11/20 ,  G06F11/22 ,  G06F13/00 ,  G06F15/16

    Abstract: PURPOSE: To detect the connection error of cables without the need of mutually physically different cables or cable connectors by making the interface logic units of respective computer elements communicate with each other and judging whether or not a redundant communication route is correctly connected between the elements. CONSTITUTION: The redundant computer processing slices 15 and 18 of a first computer processing section 3 are respectively provided with X and Y master interface logics XMIL 24 and YMIL 27. The SMIL 24 and the YMIL 27 are respectively provided with a cable detection signal generator, an element address signal generator, an element slice identification signal generator and a remote connection indicator(RCI) signal receiver. Then, erroneous cable wiring constitution is identified by cable detection signals driven from the first processing section 3 to the respective ones of processing sections 6, 9 and 12 and RCI signals driven from respective target processing slices 6, 9 and 12 to the first processing section 3 in response to address, slice and cable detection signals.

    ELECTRONIC KEYING SYSTEM AND METHOD FOR MULTIPLEX BOARD SYSTEM
    13.
    发明专利
    ELECTRONIC KEYING SYSTEM AND METHOD FOR MULTIPLEX BOARD SYSTEM 失效

    公开(公告)号：JPH04340120A

    公开(公告)日：1992-11-26

    申请号：JP10091

    申请日：1991-01-07

    Applicant: TANDEM COMPUTERS INC

    Inventor： UIRIAMU PII BUNTON ,  JIYON EMU BURAUN ,  PATORISHIA ERU HOWAITOSAIDO

    IPC: G06F3/00 ,  G06F13/40 ,  H05K1/14

    Abstract: PURPOSE: To secure the suitable unit constitution of boards by sending power turn-on signals with a special constitution connector route for respective boards and inhibiting the turn-on of power supply with an unsuitable power constitution. CONSTITUTION: The respective boards #1 and #2 have multiple circuits constituting a computer system. Diodes 21 are connected to the pins of the connector 20 on the board #2. Conduction is possible in accordance with a cord peculiar to the board #2 with the polarity of the diodes 21. Conductors 22 on the board #1 of the connector 20 are wired in accordance with a direction. The diodes 21 are arranged so that current flow toward a power controller 24 from a power source 23 through the diodes in a front direction. When the wiring of the board #1-side does not correspond to the coding of the diodes 21 on the board #2-side of the connector 20, a series route is blocked by the diodes which are inversely connected and the power source 23 is not connected to the power controller 24, the power controller 24 is not started.

    COMPUTER MEMORY SYSTEM
    15.
    发明专利
    COMPUTER MEMORY SYSTEM 失效

    公开(公告)号：JPH03135642A

    公开(公告)日：1991-06-10

    申请号：JP17609390

    申请日：1990-07-03

    Applicant: TANDEM COMPUTERS INC

    Inventor： ROBAATO DABURIYUU HOOSUTO ,  AAJIEI KEI SHIYAA ,  AI KOO YAMAMOTO

    IPC: G06F12/08 ,  G06F12/02 ,  G06F12/10

    Abstract: PURPOSE: To perform high-speed memory read and write by providing a comparator for judging whether or not a memory location indicated by an address request is included inside the plural memory locations. CONSTITUTION: In order to process a new address request 001110, row bits inside the address request 8 and the contents of virtual/physical (CAMtag) 7 are compared. In this case, the row bits inside the address request 8 are 001 and the contents of the CAMtag 7 are 101 on the other hand. Thus, since the comparator 11 indicates that a CAM error is present, it means that the newly arrived address request 8 is for a row different from the row asserted at present. Then, when the comparator 11 indicates an error, registers 6 and 7 are updated. Thus, cache fill time is reduced and a valid write band width is enlarged.

    METHOD AND DEVICE FOR PROCESSING DATA
    16.
    发明专利
    METHOD AND DEVICE FOR PROCESSING DATA 失效

    公开(公告)号：JPH03129523A

    公开(公告)日：1991-06-03

    申请号：JP18255290

    申请日：1990-07-10

    Applicant: TANDEM COMPUTERS INC

    Inventor： ROBAATO DABURIYUU HOOSUTO ,  ROBAATO ERU JIYAADEIIN

    IPC: G06F7/499 ,  G06F7/00 ,  G06F7/53 ,  G06F11/14

    Abstract: PURPOSE: To detect errors with simple constitution by giving an error signal when a first operation result for first and second operands and a second operation result for third and fourth operands are not equal. CONSTITUTION: A redundant multiplication result is transferred from a COU output register 36 to the scratch register 50b of a register file 50 or from the register to either J or K register 54 or 56 in a data device 18. At the same time, an (shifted) initial result is transferred from a scratch path (SPAD) 64 to the other J or K register 54 or 56. The contents of the two registers are exclusively OR-processed by an arithmetic and logic unit(ALU) 58. The result is monitored by a zero detection circuit 70 and a comparison processing is executed. When the error is detected, a series of other means is given and the error becomes a multiplication error. Thus, the error can be detected with simple constitution.

    METHOD AND SYSTEM FOR PROCESSING EXCEPTION
    17.
    发明专利
    METHOD AND SYSTEM FOR PROCESSING EXCEPTION 失效

    公开(公告)号：JPH03116236A

    公开(公告)日：1991-05-17

    申请号：JP13513890

    申请日：1990-05-24

    Applicant: TANDEM COMPUTERS INC

    Inventor： ROBAATO ERU JIYAADEIIN ,  SHIYANON JIEI RINCHI ,  FUIRITSUPU AARU MANERA ,  ROBAATO DABURIYUU HOOSUTO

    IPC: G06F9/38

    Abstract: PURPOSE: To simplify a system by activating an exception procedure developed for a signal instruction by a unique exception processing procedure. CONSTITUTION: An exception display test bit field generated by an ALU is connected with the input of a latched MUX 110, a control port is connected with the control field of a microcode in a level 5, and the output is connected with a second input port of an AND gate 106. The output of a first decoder DEC I flashes a pipe line and inhibits the writing operation of a level 5 when an exception condition is discovered. The MUX 110 transmits a specific exception display test bit to be tested about an instruction family during execution, and when the exception condition is generated, the AND gate 106 is opened, a microcode filed of (m) bits in a level 5 is decoded, and a control signal for executing a non-paring restarting procedure execution is generated. Thus, the system can be simplified.

    INTEGRATED CIRCUIT ARCHITECTURE OF LINEAR ARRAY WAFER SCALE
    18.
    发明专利
    INTEGRATED CIRCUIT ARCHITECTURE OF LINEAR ARRAY WAFER SCALE 失效

    公开(公告)号：JPH0369138A

    公开(公告)日：1991-03-25

    申请号：JP11567490

    申请日：1990-05-01

    Applicant: TANDEM COMPUTERS INC

    Inventor： ROBAATO DABURIYUU HOOSUTO

    IPC: H01L21/82 ,  G11C29/00 ,  H03K19/173

    Abstract: PURPOSE: To obtain a simplified architecture adapting to use to form a linear array by connecting it with a digital system array by incorporating input bus means and output bus means at boundaries in cells, and incorporating specific selecting means, logic means and control means in a cell structure. CONSTITUTION: A cell 10 is formed to have N boundaries. Each boundary has an input bus means and an output bus means. A structure of the cell 10 has a selecting means 12 corresponding to each boundary and having a plurality of selective inputs and one selective output connected to receive the input bus means and output bus means of the corresponding boundary to couple the selective output of the (N-1) boundaries to the output bus means of relative adjacent boundary to be operable to select the input bus means or the output bus means; a logic means 20 connected between the residual selecting means 12 and the output bus means of relative adjacent boundary to perform a logical function; and a control means 22 coupled to the respective means 12 to select one of a plurality of selective inputs to the respective means 12.

    DYNAMIC BURST CONTROLLER FOR DATA TRANSFER
    20.
    发明专利
    DYNAMIC BURST CONTROLLER FOR DATA TRANSFER 失效

    公开(公告)号：JPH0228860A

    公开(公告)日：1990-01-30

    申请号：JP8954889

    申请日：1989-04-07

    Applicant: TANDEM COMPUTERS INC

    Inventor： UIN EMU CHIYAN

    IPC: G06F13/36 ,  G06F13/28

    Abstract: PURPOSE: To highten a data rate while giving access for transferring data to a peripheral device of a low priority order by automatically adjusting the burst length of data transferred between a processor unit and the peripheral device. CONSTITUTION: Plural device controllers 14, 16 and 18 are connected to the processor unit 12 through an I/O bus 20. In the middle of a data transferring cycle, a device controller controlling data transfer monitors the I/O bus with respect to the generation of a request signal from another device controller. At the time of detecting the generation of the request signal and instructing that not less than one other device controllers request a data transfer cycle, a present data transferring cycle interrupts after a prescribed event. The interrupted device controller waits in some period before requesting access to the I/O bus 20 so that another peripheral device may join the data transferring cycle with the processor unit 12.

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