公开(公告)号：JPH04340120A

公开(公告)日：1992-11-26

申请号：JP10091

申请日：1991-01-07

Applicant: TANDEM COMPUTERS INC

Inventor： UIRIAMU PII BUNTON ,  JIYON EMU BURAUN ,  PATORISHIA ERU HOWAITOSAIDO

IPC: G06F3/00 ,  G06F13/40 ,  H05K1/14

Abstract: PURPOSE: To secure the suitable unit constitution of boards by sending power turn-on signals with a special constitution connector route for respective boards and inhibiting the turn-on of power supply with an unsuitable power constitution. CONSTITUTION: The respective boards #1 and #2 have multiple circuits constituting a computer system. Diodes 21 are connected to the pins of the connector 20 on the board #2. Conduction is possible in accordance with a cord peculiar to the board #2 with the polarity of the diodes 21. Conductors 22 on the board #1 of the connector 20 are wired in accordance with a direction. The diodes 21 are arranged so that current flow toward a power controller 24 from a power source 23 through the diodes in a front direction. When the wiring of the board #1-side does not correspond to the coding of the diodes 21 on the board #2-side of the connector 20, a series route is blocked by the diodes which are inversely connected and the power source 23 is not connected to the power controller 24, the power controller 24 is not started.

公开(公告)号：JPH09134336A

公开(公告)日：1997-05-20

申请号：JP14527096

申请日：1996-06-07

Applicant: TANDEM COMPUTERS INC

Inventor： ROBAATO DABURIYUU HOOSUTO ,  UIRIAMU EDOWAADO BEIKAA ,  RINDA ERIN ZARUZAARA ,  UIRIAMU PATAASON BANTON ,  RICHIYAADO DABURIYUU KATSUTSU ,  DEIBUITSUDO JIEI GAASHIA ,  JIYON SHII KURAUSU ,  SUTEIIBUN JII ROU ,  DEIBUITSUDO POORU SOONIA ,  UIRIAMU JIYOERU WATOSON ,  PATORISHIA ERU HOWAITOSAIDO

IPC: G06F11/18 ,  G06F9/52 ,  G06F11/00 ,  G06F11/10 ,  H04L1/24 ,  H04L9/14 ,  G06F15/163 ,  G06F15/16

Abstract: PROBLEM TO BE SOLVED: To provide a multiprocessor system via a single system by attaining a fault tolerant action through the fail-first and fail-functional actions. SOLUTION: The transmitting clock signals existing on a two-way link are supplied to a pair of transmitting and receiving elements in order to demarcate the clock cycles and also to receive the multi-bit words in a processing system which includes the paired transmitting and receiving elements connected to each other for communication of the multi-bit words including the multi-bit data words and multi-bit command words. Then one of paired transmitting and receiving elements transmits the data to the other element in form of a series of multi-bit data words, transmits the multi-bit data words in every clock cycle and transmits the multi-bit command words in every clock cycle and with no sequence.

公开(公告)号：JPH09128347A

公开(公告)日：1997-05-16

申请号：JP14555196

申请日：1996-06-07

Applicant: TANDEM COMPUTERS INC

Inventor： ROBAATO DABURIYUU HOOSUTO ,  UIRIAMU EDOWAADO BEIKAA ,  RANDARU JII BANTON ,  JIYON MAIKERU BURAUN ,  UIRIAMU EFU BURUTSUKAATO ,  UIRIAMU PATAASON BANTON ,  GEARII EFU KIYANBERU ,  JIYON DEIIN KOODEINTON ,  RICHIYAADO DABURIYUU KATSUTSU ,  BARII RII DOREKUSURAA ,  HARII FURANKU ERUROTSUDO ,  DANIERU ERU FUAURAA ,  DEIBUITSUDO JIEI GAASHIA ,  POORU ENU HINTEITSUKA ,  JIEFURII AI ISUWANDEII ,  DAGURASU YUUJIIN JIYUUITSUTO ,  KAATEISU UIIRAADO JIYOONZU JIY ,  JIEEMUZU SUTEIIBUNSU KURETSUKA ,  JIYON SHII KURAUSU ,  SUTEIIBUN JII ROU ,  SUUZAN SUTOON MERADEISU ,  SUTEIIBUN SHII MEIAAZU ,  DEIBUITSUDO POORU SOONIA ,  UIRIAMU JIYOERU WATOSON ,  PATORISHIA ERU HOWAITOSAIDO ,  FURANKU EI UIRIAMUSU ,  RINDA ERIN ZARUZAARA

IPC: G06F11/18 ,  G06F11/16 ,  G06F15/16 ,  G06F15/17

Abstract: PROBLEM TO BE SOLVED: To facilitate fault-tolerant operation by including a routing element coupled with the central processor and peripheral device of a subprocessing system so as to transmit data between the central processor and peripheral device of the subprocessing system. SOLUTION: Subprocessor systems 10A and 10B include central processors CPUs 12, routers 14, and plural input/output I/O packet interfaces 16 connected to many I/O devices 17 by characteristic input/output NIO buses. The MPs 18 of the subprocessor system 10A and 10B connect IEEE1149. one-test buses 17 and registers used by the MPs 18 to transmit states and control information between elements and MPs 18 to elements of the subprocessor systems through on-line access port OLAP interfaces included in the elements.