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公开(公告)号：KR1020090105115A
公开(公告)日：2009-10-07
申请号：KR1020080030382
申请日：2008-04-01
Applicant: 삼성전기주식회사
Abstract: PURPOSE: A multilayer chip capacitor is provided to low maintain an ESL(Equivalent Series Inductance) while an ESR(Equivalent Series Resistance) of a capacitor is controlled. CONSTITUTION: A multilayer chip capacitor includes a capacitor main body, a first outer electrode, a second outer electrode, a third outer electrode, and a fourth outer electrode. The capacitor main body has a first long side surface, a second long side surface, a first short side surface, and a second short side surface. The first long side surface is faced with the second long side surface. The first short side surface is faced with the second short side surface. The capacitor main body has a laminate structure in which a plurality of dielectric layers(110a) are laminated. The capacitor main body includes a first capacitor part(CR1) and a second capacitor part(CR2). The first outer electrode and the second outer electrode are formed on the first long side surface and the second long side surface. The third outer electrode and the fourth outer electrode are formed on the first short side surface and the second short side surface.
Abstract translation: 目的：在控制电容器的ESR（等效串联电阻）的同时，提供多层片式电容器以低维持ESL（等效串联电感）。 构成：多层片状电容器包括电容器主体，第一外部电极，第二外部电极，第三外部电极和第四外部电极。 电容器主体具有第一长边侧表面，第二长边表面，第一短边表面和第二短边表面。 第一长边表面面对第二长边表面。 第一短边表面面对第二短边表面。 电容器主体具有层叠多个电介质层（110a）的叠层结构。 电容器主体包括第一电容器部分（CR1）和第二电容器部分（CR2）。 第一外电极和第二外电极形成在第一长侧表面和第二长侧表面上。 第三外电极和第四外电极形成在第一短侧面和第二短边面上。
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公开(公告)号：KR1020090032671A
公开(公告)日：2009-04-01
申请号：KR1020070098102
申请日：2007-09-28
Applicant: 삼성전기주식회사
IPC: H01G4/30
Abstract: A multilayer chip capacitor and a method for controlling an electrostatic capacity thereof are provided to select a desired electrostatic capacity by connecting an external electrode to a power line without a separate multilayer chip capacitor. A multilayer chip capacitor(10) includes a main body(11), a plurality of first internal electrodes, a plurality of second internal electrodes, a plurality of first external electrodes(18a,18b), and a plurality of second external electrodes(19a,19b). The main body is made of a plurality of dielectric layers. The first internal electrodes and the second internal electrodes are arranged inside the main body by turns in between the dielectric layers, and are divided into a plurality of groups including at least a pair of first and second internal electrodes. The first external electrodes and the second external electrodes are formed on a surface of the main body. The first internal electrode and the second internal electrode of each group are respectively connected to the first external electrode and the second external electrode, and have at least two capacity values according to a selection of the first external electrode and the second external electrode connected to an external power line.
Abstract translation: 提供一种多层片状电容器及其静电电容的控制方法，通过将外部电极连接到没有单独的多层片状电容器的电源线来选择所需的静电电容。 多层片状电容器（10）包括主体（11），多个第一内部电极，多个第二内部电极，多个第一外部电极（18a，18b）和多个第二外部电极（19a） ，19B）。 主体由多个电介质层制成。 第一内部电极和第二内部电极在电介质层之间的匝内布置在主体内部，并且被分成包括至少一对第一和第二内部电极的多个组。 第一外部电极和第二外部电极形成在主体的表面上。 各组的第一内部电极和第二内部电极分别与第一外部电极和第二外部电极连接，根据与第一外部电极和第二外部电极连接的第一外部电极和第二外部电极的选择，具有至少两个电容值 外部电源线。
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公开(公告)号：KR1020080110180A
公开(公告)日：2008-12-18
申请号：KR1020070058596
申请日：2007-06-14
Applicant: 삼성전기주식회사
Abstract: A method for performing controlled ESR(Equivalent Serial Resistance) multilayer chip capacitor having low ESL(Equivalent Serial Inductance) is provided to perform stabilization of a power circuit by lining-up ESR in a wide range. A method for performing controlled ESR multilayer chip capacitor having low ESL comprises the following steps: a step for arranging an inner electrode of a first and second polarity(+,-) between dielectric layers; a step for laminating one block which has inner electrodes(1010, 1020, 1030, 1040, 1050, 1060, 1070) more than 2 consecutively arranged as top and bottom; a step for determining a mean value of total leads(1010a, 1020a, 1020b, 1030a, 1040a,1040b, 1050a, 1060a, 1060b, 1070a) of two inner electrodes which mutually faces in block; a step for determining the number of lead of each inner electrode inside the block; and a step for determining a location of the leads of each inner electrode.
Abstract translation: 提供了具有低ESL（等效串联电感）的受控ESR（等效串联电阻）多层片式电容器的方法，以通过在宽范围内排列ESR来实现电力电路的稳定。 用于执行具有低ESL的受控ESR多层片式电容器的方法包括以下步骤：在电介质层之间布置第一和第二极性（+， - ）的内部电极的步骤; 层叠一个具有连续排列为顶部和底部的内部电极（1010,1020,1030,1040,1050,1060,1070）的块的步骤; 确定相互面对的两个内部电极的总线（1010a，1020a，1020b，1030a，1040a，1040b，1050a，1060a，1060b，1070a）的平均值的步骤; 确定块内的每个内电极的引线数的步骤; 以及确定每个内部电极的引线的位置的步骤。
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公开(公告)号：KR100867505B1
公开(公告)日：2008-11-07
申请号：KR1020070095522
申请日：2007-09-19
Applicant: 삼성전기주식회사
IPC: H01L23/12
CPC classification number: H01L23/50 , H01G4/35 , H01L23/49838 , H01L2924/0002 , H01L2924/3011 , H05K1/0231 , H05K1/113 , H05K2201/0792 , H05K2201/09309 , H05K2201/0979 , H05K2201/10636 , Y02P70/611 , H01L2924/00
Abstract: A circuit board for a mounting multilayer chip capacitor and a circuit board apparatus having a multilayer chip capacitor are provided to minimize loop inductance. A substrate(35) has a mounting region for mounting a vertical mounting multilayer chip capacitor(100) which has first and second external electrode(131,132) of first polarity and a third external electrode(133) of second polarity. A first via(41) is connected to a first pad(31) by being formed in the substrate, and a second via(42) is connected to a second pad(32) by being formed in the substrate. A plurality of vias(43a,43b) are connected to a third pad(33) by being formed in the substrate.
Abstract translation: 提供了用于安装多层片状电容器的电路板和具有多层片状电容器的电路板装置，以使回路电感最小化。 基板（35）具有用于安装具有第一极性的第一和第二外部电极（131,132）和第二极性的第三外部电极（133）的垂直安装多层片状电容器（100）的安装区域。 第一通孔（41）通过形成在基板中而连接到第一焊盘（31），并且第二通孔（42）通过形成在基板中而连接到第二焊盘（32）。 多个通孔（43a，43b）通过形成在基板中而连接到第三焊盘（33）。
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公开(公告)号：KR100843434B1
公开(公告)日：2008-07-03
申请号：KR1020060092425
申请日：2006-09-22
Applicant: 삼성전기주식회사
Abstract: 본 발명에 따른 적층형 칩 커패시터는, 복수의 유전체층이 적층되어 형성되고, 서로 대향하는 제1 및 제2 측면과 서로 대향하는 제3 및 제4 측면을 갖는 커패시터 본체와; 상기 커패시터 본체 내에서 상기 유전체층에 의해 분리되어 적층된 복수의 내부 전극층과; 상기 제1 측면에 형성된 하나 이상의 제1 외부 전극과; 상기 제2 측면에 형성된 하나 이상의 제2 외부 전극을 포함한다. 상기 제1 외부 전극과 제2 외부 전극은 서로 오프셋되도록 배치되어 상기 제1 측면의 길이 방향으로 소정 간격만큼 이격되어 있다.
적층형 칩 커패시터, 외부 전극, 등가직렬 인덕턴스-
Patent Agency Ranking
公开(公告)号：KR1020070075867A
公开(公告)日：2007-07-24
申请号：KR1020060004592
申请日：2006-01-16
Applicant: 삼성전기주식회사
Abstract: A laminated ceramic capacitor with a low ESL(Equivalent Serial Inductance) and a wiring substrate are provided to satisfy characteristics as a capacitor for decoupling of an RF(Radio Frequency) circuit by lowering the ESL. A laminated ceramic capacitor with a low ESL includes a capacitor main body, a groove, an external electrode, a first internal electrode(52a), a second internal electrode(52b), and a contacting unit(53a,53b). The groove is formed vertically at a side of the capacitor main body. The external electrode is formed on the groove. The first internal electrode(52a) and the second internal electrode(52b) having current with different polarities are alternately laminated while interposing a dielectric. The contacting unit(53a,53b) is contacted to the external electrode of the groove, and formed at a side of the first internal electrode(52a) and the second internal electrode(52b).
Abstract translation: 提供具有低ESL（等效串联电感）和布线基板的层压陶瓷电容器，以满足通过降低ESL来解耦RF（射频）电路的电容器的特性。 具有低ESL的层压陶瓷电容器包括电容器主体，沟槽，外部电极，第一内部电极（52a），第二内部电极（52b）和接触单元（53a，53b）。 凹槽在电容器主体的一侧垂直地形成。 外部电极形成在槽上。 具有不同极性的电流的第一内部电极（52a）和第二内部电极（52b）交替层叠，同时插入电介质。 接触单元（53a，53b）与沟槽的外部电极接触，并形成在第一内部电极（52a）和第二内部电极（52b）的一侧。
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公开(公告)号：KR100674823B1
公开(公告)日：2007-01-26
申请号：KR1020040102609
申请日：2004-12-07
Applicant: 삼성전기주식회사
IPC: H01G4/30
Abstract: 본 발명은 적층형 캐패시터 어레이의 배선접속구조에 관한 것으로서, 적어도 2개의 전원공급라인과 접지라인이 구비된 모기판; 및, 상기 모기판에 실장되며, 마이크로 프로세싱 유닛(MPU)칩이 구비된 배선기판과 상기 배선기판 하부에 장착된 적층형 캐패시터 어레이를 포함하는 적층형 캐패시터 어레이 패키지를 포함하며, 상기 전원공급라인 및 접지라인 중 적어도 하나가 적층형 캐패시터 어레이의 도전성 비아홀을 통해 MPU칩의 단자에 연결되는 적층형 캐패시터 어레이의 배선접속구조를 제공한다.
적층형 캐패시터 어레이(Multi-Layered Chip Capacitor Array), 등가직렬인덕턴스(ESL), 디커플링 캐패시터(decoupling capacitor), 마이크로 프로세싱 유닛(MPU)-
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公开(公告)号：KR101922869B1
公开(公告)日：2018-11-28
申请号：KR1020130129364
申请日：2013-10-29
Applicant: 삼성전기주식회사
Abstract: 본발명은, 복수의제1 유전체층이적층된세라믹본체; 상기제1 유전체층을사이에두고상기세라믹본체의양 단면을통해번갈아노출되도록형성된복수의제1 및제2 내부전극을포함하는액티브층; 복수의제2 유전체층이적층되며, 상기액티브층의상부및 하부에각각형성된상부및 하부커버층; 및상기세라믹본체의양 단면에형성되며, 상기제1 및제2 내부전극과각각전기적으로연결된제1 및제2 외부전극; 을포함하며, 상기제2 유전체층의적어도일부는상기제1 유전체층보다모듈러스가큰 재료로형성된적층세라믹전자부품을제공한다.
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公开(公告)号：KR101813278B1
公开(公告)日：2017-12-28
申请号：KR1020110036197
申请日：2011-04-19
Applicant: 삼성전기주식회사
Abstract: 적층형세라믹커패시터가개시된다. 적층형세라믹커패시터는유전체층과유전체층사이에교대로적층된다수의내부전극들을포함하는세라믹소체와, 세라믹소체의외부면에고착되어다수의내부전극들과연결되는외부전극을포함하며, 외부전극이고착되는세라믹소체의면의형상은오목하게만곡된형상을가짐으로써, 외부전극과의접촉면적을증가시켜외부전극의고착강도를증가시킬수 있는효과가있다.
Abstract translation: 公开了一种多层陶瓷电容器。 多层陶瓷电容器包括：陶瓷体，其包括交替地层叠在介电层和介电层之间的多个内部电极;以及外部电极，其固定到陶瓷体的外表面并连接到多个内部电极， 陶瓷体表面的形状是凹形弯曲的，从而增加了与外部电极的接触面积以增加外部电极的接合强度。
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