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公开(公告)号：KR100814374B1
公开(公告)日：2008-03-18
申请号：KR1020060091063
申请日：2006-09-20
Applicant: 삼성전자주식회사
IPC: H01L27/115
CPC classification number: H01L29/66833 , H01L21/28282 , H01L21/31144 , H01L29/4234 , H01L29/517
Abstract: A method for fabricating an NVM(non-volatile memory) device is provided to increase a threshold voltage window of an NVM device by sufficiently avoiding formation of an undesired layer between a charge trapping layer and a blocking layer by a heat treatment. A tunnel insulation layer(102) is formed on a substrate(100) having a channel region. A charge trapping layer for trapping electrons from the channel region is formed on the tunnel insulation layer, including silicon nitride. A heat treatment is performed on the charge trapping layer at a temperature of 1000-1250 ‹C to densify the charge trapping layer. A blocking layer(108) is formed on the heat-treated charge trapping layer(106). A conductive layer is formed on the blocking layer. The conductive layer, the blocking layer, the charge trapping layer and the tunnel insulation layer are patterned to form a gate structure on the channel region. The blocking layer can include an oxide. The blocking layer can include a metal oxide having a higher dielectric constant than that of a silicon nitride.
Abstract translation: 提供一种用于制造NVM（非易失性存储器）器件的方法，以通过充分避免通过热处理在电荷俘获层和阻挡层之间形成不需要的层来增加NVM器件的阈值电压窗口。 隧道绝缘层（102）形成在具有沟道区的衬底（100）上。 在隧道绝缘层上形成用于从沟道区捕获电子的电荷捕获层，包括氮化硅。 在1000-1250℃的温度下对电荷捕获层进行热处理以使电荷捕获层致密化。 在热处理电荷捕获层（106）上形成阻挡层（108）。 在阻挡层上形成导电层。 将导电层，阻挡层，电荷俘获层和隧道绝缘层图案化以在沟道区上形成栅极结构。 阻挡层可以包括氧化物。 阻挡层可以包括具有比氮化硅更高的介电常数的金属氧化物。
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公开(公告)号：KR1020070093744A
公开(公告)日：2007-09-19
申请号：KR1020060024042
申请日：2006-03-15
Applicant: 삼성전자주식회사
IPC: H01L21/31
CPC classification number: H01L21/28194 , H01L21/02046 , H01L21/0228 , H01L21/28185 , H01L21/324
Abstract: A method for forming a semiconductor device with a high-k dielectric layer is provided to improve remarkably leakage current characteristics by compensating the high-k dielectric layer for the depletion of oxygen using an ion implantation on the high-k dielectric layer. A high-k dielectric layer is formed on a substrate by using a first ALD(Atomic Layer Deposition)(S150). A doping layer containing ions is formed on the high-k dielectric layer by using a second ALD(S160). A doped high-k dielectric layer is completed on the resultant structure by using a heat treatment(S170). The first ALD is performed by using sequentially a high-k source gas and an oxygen source gas.
Abstract translation: 提供一种用于形成具有高k电介质层的半导体器件的方法，以通过使用高k电介质层上的离子注入补偿用于耗尽氧的高k电介质层来改善显着的漏电流特性。 通过使用第一ALD（原子层沉积）（S150）在基板上形成高k电介质层。 通过使用第二ALD在高k电介质层上形成含有离子的掺杂层（S160）。 通过使用热处理在所得结构上完成掺杂的高k电介质层（S170）。 通过依次使用高k源气体和氧源气体来执行第一ALD。
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公开(公告)号：KR1020060097901A
公开(公告)日：2006-09-18
申请号：KR1020050018795
申请日：2005-03-07
Applicant: 삼성전자주식회사
CPC classification number: C25D17/10 , C25D7/123 , C25D17/001 , H01L21/2885
Abstract: 도금 처리 공정에서 사용되는 도금 처리 장치가 제공된다. 도금 처리 장치는 도금액이 공급되며 도금액 입구 및 도금액 출구가 형성되어 있는 도금조, 도금조 내에 설치되어 있는 애노드, 애노드와 소정 간격 이격되어 대향하며 피도금물이 설치되는 캐소드 및 애노드와 캐소드 사이에 설치되는 도전체를 포함한다.
도금 처리 장치, 도전체, 애노드, 캐소드, 피도금물, 도금층-
公开(公告)号：KR1020160135010A
公开(公告)日：2016-11-24
申请号：KR1020150067546
申请日：2015-05-14
Applicant: 삼성전자주식회사
IPC: H01L29/78 , H01L21/205
CPC classification number: H01L29/7851 , H01L29/0847 , H01L29/165 , H01L29/66545 , H01L29/7848 , H01L29/7849
Abstract: 반도체소자는, 기판상에제공되고일 방향으로연장되는핀 구조체, 상기핀 구조체를가로지르는게이트전극, 상기게이트전극양 측의상기핀 구조체상에제공되는소스/드레인영역들, 및상기소스/드레인영역들의각각과상기핀 구조체사이의배리어층을포함한다. 상기핀 구조체는상기기판과다른격자상수를갖는물질을포함한다. 상기핀 구조체, 상기소스/드레인영역들, 및상기배리어층은게르마늄을포함한다. 상기배리어층내 게르마늄농도는상기핀 구조체내 게르마늄농도보다크고, 상기소스/드레인영역들각각내 게르마늄의최대농도보다작다.
Abstract translation: 半导体器件包括在衬底上并沿第一方向延伸的翅片结构，在翅片结构上交叉的栅电极，在栅电极的相对侧的翅片结构上的源/漏区和鳍结构之间的阻挡层 和源极/漏极区域中的每一个。 翅片结构包括具有与衬底的晶格常数不同的晶格常数的材料，鳍结构，源/漏区和阻挡层包括锗，并且阻挡层中的锗浓度大于翅片结构中的锗浓度 并且在每个源极/漏极区域中小于最大锗浓度。
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公开(公告)号：KR1020160125208A
公开(公告)日：2016-10-31
申请号：KR1020150056097
申请日：2015-04-21
Applicant: 삼성전자주식회사
IPC: H01L29/78
CPC classification number: H01L27/0886 , H01L21/823425 , H01L21/823431 , H01L29/0649 , H01L29/0847 , H01L29/161 , H01L29/41791
Abstract: 기판상에서로평행하게연장하는핀 액티브영역들, 상기핀 액티브영역들을정의하는아이솔레이션영역, 상기핀 액티브영역들과수직으로교차하고서로평행하게연장하는게이트패턴들, 상기게이트패턴들사이의상기핀 액티브영역들상의소스/드레인영역들및 상기핀 액티브영역들의측면들과접하고, 상기핀 액티브영역들사이의상기아이솔레이션영역의표면을덮는핀 액티브스페이서들을포함하고, 상기핀 액티브스페이서들의최상부레벨들은상기핀 액티브영역들과상기소스/드레인영역들간의경계면들보다높고, 및상기아이솔레이션영역의표면은상기소스/드레인영역들의하면들보다낮은반도체소자가설명된다.
Abstract translation: 半导体器件可以包括在衬底上彼此平行延伸的翅片有源区域，翅片有源区域之间的隔离区域，与翅片有源区域相交并且彼此平行延伸的栅极图案，翅片有源区域之间的源极/漏极区域在 所述栅极图案和鳍状有源区间隔物接触所述翅片有源区域的侧表面并形成在所述鳍片活动区域之间的所述隔离区域的表面上。 翅片有源区间隔物的最上层可以高于翅片有源区和源极/漏极区之间的界面。 隔离区域的上表面可以低于源/漏区域的底表面。
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Patent Agency Ranking
公开(公告)号：KR1020090067020A
公开(公告)日：2009-06-24
申请号：KR1020080057959
申请日：2008-06-19
Applicant: 삼성전자주식회사
IPC: H01L21/8247
Abstract: A nonvolatile memory device is provided to reduce damage and power consumption by minimizing loss of charges in a program operation. A nonvolatile memory device includes a control gate electrode(150), a charge storage insulating layer(120), a tunnel insulating layer(110), a blocking insulating layer(140), and a material layer(130). The control gate electrode is arranged on the substrate(100). The charge storage insulating layer is inserted between the control gate electrode and the substrate. The tunnel insulating layer is inserted between the charge storage insulating layer and the substrate. The blocking insulating layer is inserted between the charge storage insulating layer and the control gate electrode. The material layer is inserted between the tunnel insulating layer and the blocking insulation layer. The material layer has an energy level corresponding to a bottom of a potential well.
Abstract translation: 提供了一种非易失性存储器件，用于通过使程序操作中的电荷损失最小化来减少损坏和功耗。 非易失性存储器件包括控制栅电极（150），电荷存储绝缘层（120），隧道绝缘层（110），阻挡绝缘层（140）和材料层（130）。 控制栅电极配置在基板（100）上。 电荷存储绝缘层插入在控制栅电极和衬底之间。 隧道绝缘层插入电荷存储绝缘层和基片之间。 阻挡绝缘层插入电荷存储绝缘层和控制栅电极之间。 材料层插入在隧道绝缘层和阻挡绝缘层之间。 材料层具有对应于势阱的底部的能级。
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公开(公告)号：KR1020080087586A
公开(公告)日：2008-10-01
申请号：KR1020070030044
申请日：2007-03-27
Applicant: 삼성전자주식회사
IPC: H01L21/8247 , H01L21/324
Abstract: A method for manufacturing a semiconductor device is provided to secure a TANOS structure having an improved retention characteristic by reducing an EOT(Equivalent Oxide Thickness) of an Al2O3 layer as a blocking layer. A semiconductor device(10) is a flash memory device including a TANOS structure. The TANOS structure is formed by stacking sequentially a SiO2 layer(30), a Si3N4 layer(40), a Al2O3 layer(50), and a TaN layer(60). The SiO2 layer has a function of a tunneling layer. The Si3N4 layer has a function of a trap layer. The Al2O3 layer has a function of a blocking layer. In the TANOS structure, the voltage of the Al2O3 layer as the blocking layer is lowered by reducing an EOT of the Al2O3 layer, to improve characteristics of the Al2O3 layer.
Abstract translation: 提供一种制造半导体器件的方法，通过降低作为阻挡层的Al 2 O 3层的EOT（等效氧化物厚度）来确保具有改善的保持特性的TANOS结构。 半导体器件（10）是包括TANOS结构的闪存器件。 TANOS结构依次层叠SiO 2层（30），Si 3 N 4层（40），Al 2 O 3层（50）和TaN层（60）。 SiO 2层具有隧道层的功能。 Si3N4层具有陷阱层的功能。 Al 2 O 3层具有阻挡层的功能。 在TANOS结构中，作为阻挡层的Al 2 O 3层的电压通过降低Al 2 O 3层的EOT而降低，以改善Al 2 O 3层的特性。
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公开(公告)号：KR100823713B1
公开(公告)日：2008-04-21
申请号：KR1020060086593
申请日：2006-09-08
Applicant: 삼성전자주식회사
IPC: H01L27/115 , H01L21/8247
CPC classification number: H01L21/28282 , H01L29/4234 , H01L29/513 , H01L29/792
Abstract: 불휘발성 메모리 장치 및 이를 제조하는 방법에서, 채널 영역을 갖는 기판 상에 터널 절연막, 전하 트랩핑 막, 유전막 및 도전막이 순차적으로 형성된다. 게이트 전극은 상기 도전막을 패터닝함으로써 형성되며, 상기 게이트 전극의 측면들에는 스페이서가 형성된다. 유전막 패턴, 전하 트랩핑 막 패턴 및 터널 절연막 패턴은 상기 스페이서를 식각 마스크로서 사용하는 이방성 식각에 의해 상기 채널 영역 상에 형성된다. 상기 전하 트랩핑 막 패턴의 측면 부위들은 등방성 식각에 의해 제거되며, 이에 따라 상기 전하 트랩핑 막 패턴은 감소된 폭을 갖는다. 따라서, 상기 전하 트랩핑 막 패턴 내에 트랩된 전자들의 이동이 방지될 수 있으며, 상기 불휘발성 메모리 장치의 고온 스트레스 특성이 개선될 수 있다.
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公开(公告)号：KR1020080016398A
公开(公告)日：2008-02-21
申请号：KR1020060104683
申请日：2006-10-26
Applicant: 삼성전자주식회사
IPC: H01L27/115
CPC classification number: H01L29/7923 , H01L29/4234 , H01L21/28282
Abstract: A semiconductor memory device including a charge trap layer is provided to increase the magnitude and the speed of threshold voltage by using the charge trap layer including a first and second nitride layers. A tunnel insulating layer is arranged on a semiconductor substrate(100). A charge trap layer(120c) is arranged on the tunnel insulating layer. The charge trap layer is formed with a first and second nitride layers(122,124). The first nitride layer has high hole trap density. The second nitride has low hole trap density. A shielding layer is formed on the charge trap layer in order to cover an upper surface of the charge trap layer. The energy band value difference between the first nitride layer and the tunnel insulating layer in a balance band is 2-3 eV. The energy band value difference between the second nitride layer and the tunnel insulating layer in a balance band is 1-1.5 eV.
Abstract translation: 提供包括电荷陷阱层的半导体存储器件，以通过使用包括第一和第二氮化物层的电荷陷阱层来增加阈值电压的幅度和速度。 隧道绝缘层布置在半导体衬底（100）上。 电荷陷阱层（120c）布置在隧道绝缘层上。 电荷陷阱层形成有第一和第二氮化物层（122,124）。 第一氮化物层具有高的阱陷阱密度。 第二氮化物具有低的阱陷阱密度。 为了覆盖电荷陷阱层的上表面，在电荷陷阱层上形成屏蔽层。 平衡带中的第一氮化物层和隧道绝缘层之间的能带差为2-3eV。 平衡带中的第二氮化物层和隧道绝缘层之间的能带差为1-1.5eV。
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公开(公告)号：KR100763535B1
公开(公告)日：2007-10-05
申请号：KR1020060086600
申请日：2006-09-08
Applicant: 삼성전자주식회사
IPC: H01L21/8247 , H01L27/115
CPC classification number: H01L29/66833 , H01L21/28141 , H01L21/28273 , H01L21/28282 , H01L29/4234
Abstract: A method for manufacturing a nonvolatile memory device is provided to improve threshold voltage and breakdown voltage characteristics by using a charge trapping pattern composed of silicon nitride and hafnium aluminum oxide. A tunnel insulating layer is formed on a substrate(100) with a channel region(100a). A charge trapping layer is formed on the tunnel insulating layer to trap electrons from the channel region. The charge trapping layer is composed of a silicon nitride layer and a hafnium aluminum oxide layer. A dielectric film is formed on the charge trapping layer. A conductive layer is formed on the dielectric film. A gate structure(150) composed of a control gate electrode, a dielectric pattern(140), a charge trapping pattern(142) and a tunnel insulating pattern is formed on the channel region by patterning selectively the conductive layer, the dielectric film, the charge trapping layer and the tunnel insulating layer.
Abstract translation: 提供一种用于制造非易失性存储器件的方法，通过使用由氮化硅和氧化铪铝构成的电荷捕获图案来提高阈值电压和击穿电压特性。 在具有通道区域（100a）的基板（100）上形成隧道绝缘层。 在隧道绝缘层上形成电荷俘获层，以从沟道区捕获电子。 电荷捕获层由氮化硅层和铪铝氧化物层组成。 在电荷捕获层上形成介电膜。 在电介质膜上形成导电层。 通过图案化导电层，电介质膜，电介质图案，在沟道区域上形成由控制栅电极，电介质图案（140），电荷俘获图案（142）和隧道绝缘图案构成的栅极结构（150） 电荷捕获层和隧道绝缘层。
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