公开(公告)号：KR1020090095096A

公开(公告)日：2009-09-09

申请号：KR1020080020200

申请日：2008-03-04

Applicant: 삼성전자주식회사 ,  재단법인서울대학교산학협력재단

Inventor： 김덕기 ,  유하영 ,  주영창 ,  성정헌 ,  황수정 ,  정성엽

IPC: H01L21/8242 ,  H01L27/108

CPC classification number: H01L27/101 ,  G11C11/5692

Abstract: An OTP(One Time Programmable) memory device using multi plug, and a manufacturing and operating method thereof are provided to store data more than 2 bit by connecting four or more plugs between a link and a cathode. A link(44) is connected to an anode(42). A first connection unit connects the link and a cathode(40). The link and anode are included in a position lower than the cathode. The link and the anode are included in a position higher than the cathode. The cathode, the anode, the link, and the first connection unit are included in the same plane. The first connection unit includes at least one plug.

Abstract translation: 提供使用多插头的OTP（一次可编程）存储器件及其制造和操作方法，以通过在链路和阴极之间连接四个或更多个插头来存储超过2位的数据。 连接件（44）连接到阳极（42）。 第一连接单元连接连杆和阴极（40）。 链路和阳极被包括在比阴极低的位置。 链路和阳极被包括在比阴极高的位置。 阴极，阳极，连接件和第一连接单元包括在同一平面内。 第一连接单元包括至少一个插头。

公开(公告)号：KR1020090090161A

公开(公告)日：2009-08-25

申请号：KR1020080015468

申请日：2008-02-20

Applicant: 삼성전자주식회사

Inventor： 황수정 ,  김덕기 ,  성정헌 ,  송이헌 ,  최혁순

IPC: H01L21/82

CPC classification number: G11C17/16 ,  H01L23/5256 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An electrical fuse device is provided to solve the degradation of productivity due to the defect of a part of cells by replacing the defective cell with a redundancy cell. In an electrical fuse device, a cathode(100) and an anode(200) are separated from each other. A fuse link(150) connects the cathode and the anode. The fuse link comprises a multi-metal layer(L1,L2) structure including a first metal layer and a second metal layer. The cathode and anode have a laminated structure same as that of the fuse link, and the fuse link has a weak point on which electrical cutting is more facilitated the other region.

Abstract translation: 提供一种电熔丝装置，通过用冗余电池代替缺陷电池来解决由于一部分电池的缺陷导致的生产率的降低。 在电熔丝装置中，阴极（100）和阳极（200）彼此分离。 熔丝连接（150）连接阴极和阳极。 熔断体包括包括第一金属层和第二金属层的多金属层（L1，L2）结构。 阴极和阳极具有与熔断体相同的层叠结构，并且熔断体具有弱点，在其上更方便电切割其它区域。

公开(公告)号：KR1020090039063A

公开(公告)日：2009-04-22

申请号：KR1020070104475

申请日：2007-10-17

Applicant: 삼성전자주식회사

Inventor： 박주희 ,  성정헌

IPC: G11C16/26 ,  G11C16/24

CPC classification number: G11C16/0483 ,  G11C16/10 ,  G11C16/24 ,  G11C16/26

Abstract: A non-volatile memory device is provided to sense a bit lien voltage by using a sensing transistor having a high threshold voltage. A sensing circuit(300) determines the erase state or the programming condition of a target memory cell transistor. A sensing circuit comprises a sensing transistor(360) and a gate receiving the voltage of a bit line while having high threshold voltage. The threshold voltage of the sensing transistor is lower than the voltage applied to the bit line for reading connected to the transistor of the target memory cell. The threshold voltage of the sensing transistor is higher than the saturation voltage level of the bit line for reading. The sensing transistor is turned on the erase state of the transistor of the target memory cell transistor.

Abstract translation: 提供非易失性存储器件以通过使用具有高阈值电压的感测晶体管来感测位留置电压。 感测电路（300）确定目标存储单元晶体管的擦除状态或编程状态。 感测电路包括感测晶体管（360）和接收位线的电压同时具有高阈值电压的栅极。 感测晶体管的阈值电压低于施加到连接到目标存储器单元的晶体管的读取位线的电压。 感测晶体管的阈值电压高于用于读取的位线的饱和电压电平。 感测晶体管导通目标存储单元晶体管的晶体管的擦除状态。

公开(公告)号：KR1020090037743A

公开(公告)日：2009-04-16

申请号：KR1020070103238

申请日：2007-10-12

Applicant: 삼성전자주식회사

Inventor： 설광수 ,  박상진 ,  성정헌 ,  최상무

IPC: H01L21/302 ,  H01L21/8247 ,  H01L27/115

CPC classification number: H01L21/28273 ,  H01L21/302 ,  H01L27/11521

Abstract: A method for etching an aluminum oxide and a method for manufacturing a flash memory device is provided to prevent deterioration of a tunneling insulating layer due to plasma. A tunneling insulating layer(21), a charge storage layer(23), a blocking insulation layer(25), and a control gate electrode(27) are formed on the top of a substrate(11). A mask pattern is formed by using a photolithography of a region where a word line of the laminated structure is formed. A source/drain region are formed by doping a predetermined conductive on the substrate. A plurality of memory cells is discontinuously arranged in the word line in a row, and the partial domain of the aluminum oxide layer is exposed through the opened domain(30a) of the mask pattern. The part of the gate electrode corresponding to the opened region is removed.

Abstract translation: 提供蚀刻氧化铝的方法和制造闪速存储器件的方法，以防止由于等离子体引起的隧穿绝缘层的劣化。 在基板（11）的顶部形成有隧道绝缘层（21），电荷存储层（23），阻挡绝缘层（25）和控制栅电极（27）。 通过使用形成层叠结构的字线的区域的光刻法形成掩模图案。 通过在衬底上掺杂预定导电来形成源/漏区。 多个存储单元被连续排列在字线的一行中，并且氧化铝层的部分区域通过掩模图案的开放域（30a）露出。 去除与开放区域对应的栅电极的部分。

公开(公告)号：KR1020090008620A

公开(公告)日：2009-01-22

申请号：KR1020070071701

申请日：2007-07-18

Applicant: 삼성전자주식회사

Inventor： 성정헌 ,  설광수 ,  신웅철 ,  박상진 ,  최상무

IPC: H01L21/8242 ,  H01L21/336 ,  H01L27/108 ,  B82Y10/00

CPC classification number: H01L27/108 ,  G11C11/404 ,  H01L29/4234 ,  H01L29/792

Abstract: A capacitorless DRAM and an operating method thereof are provided to prevent deterioration of a tunnel insulating layer and to suppress read disturbance by implementing a charge trap type capacitorless DRAM. A gate stack(200) is positioned on a substrate(100). A tunnel insulating layer(10), a first charge trap layer(20), an interlayer insulating layer(30), a second charge trap layer(40), a blocking insulating layer(50) and a gate electrode(60) are laminated on the gate stack successively. A source(300a) and a drain(300b) are formed on the substrate of both sides of the gate stack. The gate stack with the source and the drain comprises the transistor. The gate stack provides a data storage.

Abstract translation: 提供无电容DRAM及其操作方法以防止隧道绝缘层的劣化，并通过实施电荷陷阱型无电容器DRAM来抑制读取干扰。 栅极堆叠（200）位于衬底（100）上。 隧道绝缘层（10），第一电荷陷阱层（20），层间绝缘层（30），第二电荷陷阱层（40），阻挡绝缘层（50）和栅电极（60） 依次在门堆上。 源极（300a）和漏极（300b）形成在栅极堆叠的两侧的基板上。 具有源极和漏极的栅极叠层包括晶体管。 门堆栈提供数据存储。

公开(公告)号：KR1020080094232A

公开(公告)日：2008-10-23

申请号：KR1020070038387

申请日：2007-04-19

Applicant: 삼성전자주식회사

Inventor： 김원주 ,  박윤동 ,  이승훈 ,  김석필 ,  현재웅 ,  성정헌 ,  이태희

IPC: G11C16/02 ,  G11C16/24

CPC classification number: H01L27/11521 ,  G11C16/0483 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11565 ,  H01L27/11568

Abstract: A non-volatile memory device and a method of operating the same are provided to perform reliable operation without using channel boosting. A plurality of memory transistors(Tm) are arranged as a NAND string(S) on a semiconductor substrate. A string selection transistor(Tss) and a ground selection transistor are arranged on the semiconductor substrate on both ends of the plurality of memory transistors. A bit line(BL) is electrically connected to the semiconductor substrate and a gate electrode of the ground selection transistor. The bit line and the gate electrode of the ground selection transistor are electrically connected by a contact plug on the semiconductor substrate.

Abstract translation: 提供了一种非易失性存储器件及其操作方法，以在不使用通道升压的情况下执行可靠的操作。 多个存储晶体管（Tm）被配置为半导体衬底上的NAND串（S）。 串联选择晶体管（Tss）和接地选择晶体管布置在多个存储晶体管两端的半导体衬底上。 位线（BL）电连接到半导体衬底和接地选择晶体管的栅电极。 接地选择晶体管的位线和栅电极通过半导体衬底上的接触插塞电连接。

公开(公告)号：KR1020090102555A

公开(公告)日：2009-09-30

申请号：KR1020080028068

申请日：2008-03-26

Applicant: 삼성전자주식회사 ,  재단법인서울대학교산학협력재단

Inventor： 황수정 ,  유하영 ,  김덕기 ,  성정헌 ,  주영창 ,  정성엽

IPC: H01L23/62

CPC classification number: H01L23/5256 ,  H01L2924/0002 ,  H01L2924/00

Abstract: PURPOSE: An electrical fuse device and method of operating the same are provided to use the existing processing of semiconductor device using the material of the metal gate of the cell region or the metal wiring. CONSTITUTION: The electrical fuse device includes the cathode(100) and the anode(200), and the fuse link(150). The cathode is separated from the anode. The fuse link connects a cathode and anode. The fuse link includes laminated two metal layers. The number of the metal layer which becomes blowing is changed according to the voltage applied in the fuse link and the intensity.

Abstract translation: 目的：提供一种电熔丝装置及其操作方法，以使用半导体器件的现有处理，其使用电池区域的金属栅极或金属布线的材料。 构成：电熔丝装置包括阴极（100）和阳极（200）以及熔断体（150）。 阴极与阳极分离。 熔断体连接阴极和阳极。 熔断体包括层压的两层金属层。 根据施加在熔断体中的电压和强度，变成吹塑的金属层的数量变化。

公开(公告)号：KR1020090027140A

公开(公告)日：2009-03-16

申请号：KR1020080071896

申请日：2008-07-23

Applicant: 삼성전자주식회사

Inventor： 설광수 ,  박상진 ,  최기환 ,  성정헌 ,  최상무

IPC: G11C16/34 ,  G11C16/12 ,  G11C16/10

CPC classification number: G11C16/3459 ,  G11C11/5628 ,  G11C16/0483 ,  G11C16/12

Abstract: A programming method of a non volatile memory device is provided to prevent an over program by saturating a threshold voltage within a fast time. A programming method of a non volatile memory device comprises the following steps: a step for supplying a program voltage to a memory cell(S10); a step for supplying a supplement pulse in order to stabilize a charge after supplying the program voltage(S30); a step for supplying a recovery voltage to the memory cell after supplying the supplement pulse(S40); and a step for supplying a verification voltage after supplying the recovery voltage(S50).

Abstract translation: 提供了非易失性存储器件的编程方法，以通过在快速时间内饱和阈值电压来防止过度程序。 非易失性存储器件的编程方法包括以下步骤：向存储器单元提供编程电压的步骤（S10）; 提供辅助脉冲以便在提供编程电压之后稳定电荷的步骤（S30）; 在提供补充脉冲之后，向存储单元提供恢复电压的步骤（S40）; 以及在提供恢复电压之后提供验证电压的步骤（S50）。

公开(公告)号：KR1020090022191A

公开(公告)日：2009-03-04

申请号：KR1020070087312

申请日：2007-08-29

Applicant: 삼성전자주식회사

Inventor： 박상진 ,  설광수 ,  성정헌

IPC: G11C16/34 ,  G11C16/10 ,  G11C16/12

CPC classification number: G11C16/0483 ,  G11C16/10 ,  G11C16/3454

Abstract: A programming method of a non volatile memory device is provided to saturate a threshold voltage within a fast time and to hasten stabilization of a charge by adding a perturbation pulse. In a first programming step(S100), a program voltage is supplied to a memory cell, and is verified by a first verification voltage. A perturbation pulse for hastening stabilization of a charge is supplied to the memory cell passing verification using the first verification voltage(S200). After the perturbation pulse is supplied, the program voltage is verified by a second verification voltage larger than the first verification voltage(S300). When the program voltage does not pass the verification using the second verification voltage, a program voltage is supplied to the memory cell, receives a perturbation pulse, and is verified by the second verification voltage again(S500).

Abstract translation: 提供了一种非易失性存储器件的编程方法，以在快速时间内使阈值电压饱和，并通过加入扰动脉冲来加速电荷的稳定。 在第一编程步骤（S100）中，将编程电压提供给存储单元，并通过第一验证电压进行验证。 用于加速电荷稳定的扰动脉冲被提供给使用第一验证电压的存储器单元通过验证（S200）。 在提供扰动脉冲之后，通过大于第一验证电压的第二验证电压验证编程电压（S300）。 当编程电压不通过使用第二验证电压的验证时，将编程电压提供给存储单元，接收扰动脉冲，并再次通过第二验证电压进行验证（S500）。

公开(公告)号：KR1020090022170A

公开(公告)日：2009-03-04

申请号：KR1020070087290

申请日：2007-08-29

Applicant: 삼성전자주식회사

Inventor： 최상무 ,  설광수 ,  신웅철 ,  박상진 ,  이은하 ,  성정헌

IPC: H01L21/316 ,  H01L21/8247 ,  H01L27/115 ,  B82Y40/00

CPC classification number: H01L21/28282 ,  H01L21/02178 ,  H01L21/02263 ,  H01L21/02356 ,  H01L21/02362 ,  H01L21/31604 ,  H01L21/3162 ,  H01L21/28141

Abstract: A method for forming aluminum oxide layer and a method for manufacturing a charge trap memory device using the same are provided to prevent a defect like the warpage of the substrate by reducing a temperature for forming the aluminum oxide layer by using an auxiliary layer. An amorphous aluminum oxide layer(12a) is formed in a lower layer(10). A crystalline sacrificial layer is formed on the amorphous aluminum oxide layer. The amorphous aluminum oxide layer is crystallized. The lower layer is made of the charge storage material. The amorphous chromium oxide layer forms a chromium oxide layer(14) having an alpha crystal structure by the first thermal processing. The charge storage material is the silicon nitride. The amorphous auxiliary layer is formed on the amorphous aluminum oxide layer. The densification process for the amorphous aluminum oxide layer is performed before the crystalline auxiliary layer is formed.

Abstract translation: 提供一种形成氧化铝层的方法以及使用该氧化铝层的电荷阱存储装置的制造方法，通过使用辅助层降低形成氧化铝层的温度来防止像基板的翘曲那样的缺陷。 在下层（10）中形成无定形氧化铝层（12a）。 在非晶态氧化铝层上形成晶体牺牲层。 无定形氧化铝层结晶。 下层由电荷存储材料制成。 无定形氧化铬层通过第一次热处理形成具有α晶体结构的氧化铬层（14）。 电荷存储材料是氮化硅。 无定形辅助层形成在无定形氧化铝层上。 无定形氧化铝层的致密化处理在形成结晶性辅助层之前进行。