公开(公告)号：KR1020160051376A

公开(公告)日：2016-05-11

申请号：KR1020140151278

申请日：2014-11-03

Applicant: 삼성전자주식회사

Inventor： 김진남 ,  마츠다,츠카사 ,  김락환 ,  김병희 ,  이내인 ,  이종진

IPC: H01L21/60 ,  H01L21/28

CPC classification number: H01L23/485 ,  H01L21/7684 ,  H01L21/76846 ,  H01L21/76849 ,  H01L21/76882 ,  H01L23/49822 ,  H01L23/49866 ,  H01L23/5226 ,  H01L23/53209 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53266 ,  H01L23/53276 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

Abstract: 금속배선의상면모양조절을통한, 금속배선의일렉트로마이그레이션내성을향상시킴으로써, 신뢰성이개선될수 있는반도체장치를제공하는것이다. 상기반도체장치는기판상에, 제1 트렌치를포함하는제1 층간절연막, 상기제1 트렌치의측벽및 바닥면을따라서형성되고, 노블금속(noble metal)을포함하는제1 라이너막으로, 상기노블금속은 IUPAC(International Union of Pure and Applied Chemistry)의번호붙이기를따르는주기율표의 5 주기및 6 주기에속하고, 8 내지 10 그룹에속하는제1 라이너막, 및상기제1 라이너막상에, 상기제1 트렌치를채우는제1 금속배선으로, 상기제1 금속배선의상면은상기제1 트렌치의바닥면을향해볼록한모양을갖는제1 금속배선을포함한다

Abstract translation: 本发明提供一种能够通过控制金属线的上部形状来提高金属线的电迁移公差，提高可靠性的半导体装置。 半导体器件包括：第一层间绝缘膜，包括在衬底上的第一沟槽; 沿着第一沟槽的侧壁和地板表面形成的第一衬里膜，并且包括贵金属，其中贵金属属于周期表的周期5和6，符合国际上纯净和应用的联合的编号规则 化学（IUPAC），也属于8至10组; 以及第一金属线，其用第一沟槽填充第一衬垫膜，并且其上表面朝向第一沟槽的地板表面凸出。

公开(公告)号：KR1020150073595A

公开(公告)日：2015-07-01

申请号：KR1020130161485

申请日：2013-12-23

Applicant: 삼성전자주식회사

Inventor： 백종민 ,  라상호 ,  유우경 ,  안상훈 ,  이내인 ,  김기철 ,  이전일

IPC: H01L21/28

CPC classification number: H01L23/53238 ,  H01L21/7682 ,  H01L21/76834 ,  H01L21/7684 ,  H01L21/76843 ,  H01L21/76849 ,  H01L21/76879 ,  H01L21/76883 ,  H01L23/5222 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/53223 ,  H01L23/53266 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2221/1063 ,  H01L2924/0002 ,  H01L2924/00

Abstract: 반도체소자의배선구조물및 그형성방법에서, 배선구조물은기판상에제1 절연막이구비된다. 상기제1 절연막상에는, 금속패턴들및 금속패턴들의측벽및 저면을둘러싸는베리어금속패턴들을포함하는배선패턴들이구비된다. 상기배선패턴들과직접접촉하면서상기배선패턴들상부면을덮고, 하부막에따라성막특성이다른물질을포함하는보호막패턴들이구비된다. 상기배선패턴들사이에고립된에어갭을생성하면서상기보호막패턴상에는제2 절연막이구비된다. 상기반도체소자의배선구조물은에어갭이구비됨으로써기생커패시턴스가감소되고, 금속패턴의손상이감소되어저저항을갖는다.

Abstract translation: 在半导体器件的布线结构及其形成方法中，布线结构包括在基板上的第一绝缘层。 在第一绝缘层上形成有金属图案和阻挡金属图案的围绕金属图案的下侧和侧壁的布线图案。 形成与布线图案直接接触的保护层图案，覆盖布线图案的上侧，并且包括根据下层具有不同膜特性的材料。 在布线图案之间产生隔离的气隙，并且在保护图案上形成第二绝缘层。 半导体器件的布线结构通过包括气隙来减小寄生电容，并且通过减少对金属图案的损伤而具有低电阻。

公开(公告)号：KR1020130136328A

公开(公告)日：2013-12-12

申请号：KR1020120060048

申请日：2012-06-04

Applicant: 삼성전자주식회사

Inventor： 신동석 ,  김명선 ,  남성진 ,  박판귀 ,  정회성 ,  이내인

IPC: H01L29/78 ,  H01L21/336

CPC classification number: H01L27/1104 ,  H01L21/02532 ,  H01L21/02636 ,  H01L21/28247 ,  H01L21/30604 ,  H01L21/823807 ,  H01L21/823814 ,  H01L27/088 ,  H01L27/1116 ,  H01L29/0847 ,  H01L29/1083 ,  H01L29/16 ,  H01L29/161 ,  H01L29/165 ,  H01L29/45 ,  H01L29/513 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/66575 ,  H01L29/6659 ,  H01L29/66636 ,  H01L29/7827 ,  H01L29/7833 ,  H01L29/7834 ,  H01L29/7845 ,  H01L29/7848 ,  H01L29/785 ,  H01L29/78696

Abstract: First and second active zones are limited on a substrate which has a first area and a second area having higher pattern density than the first area. A first gate electrode is formed in the first active zone. A first trench is formed in the first active zone. A first strain-inducing pattern is formed in the first trench. A second gate electrode is formed in the second active area. A second trench is formed in the second active zone. A second strain-inducing pattern is formed in the second trench. The first active zone has a first ∑-shape. The second active zone has a second ∑-shape. When defining: a first vertical line which is perpendicular to the substrate and passes the side of the first gate electrode; a second vertical line which is perpendicular to the substrate and passes the side of the second gate electrode; a first horizontal distance which is the closest distance between the first vertical line and the first trench; and a second horizontal distance which is the closest distance between the second vertical line and the second trench, a difference between the first horizontal distance and the second horizontal distance is 1 nm or less.

Abstract translation: 第一和第二活性区限制在具有第一区域和具有比第一区域更高图案密度的第二区域的基底上。 第一栅电极形成在第一有源区中。 在第一活动区域中形成第一沟槽。 在第一沟槽中形成第一应变诱导图案。 第二栅电极形成在第二有源区中。 在第二活动区域中形成第二沟槽。 在第二沟槽中形成第二应变诱导图案。 第一活动区域具有第一Σ形状。 第二活动区域具有第二Σ形状。 当限定：垂直于衬底并通过第一栅电极的一侧的第一垂直线; 第二垂直线，其垂直于所述衬底并通过所述第二栅电极的一侧; 第一水平距离，其是第一垂直线和第一沟槽之间的最近距离; 以及第二水平距离，其是第二垂直线和第二沟槽之间的最近距离，第一水平距离和第二水平距离之间的差为1nm或更小。

公开(公告)号：KR1020100088854A

公开(公告)日：2010-08-11

申请号：KR1020090007980

申请日：2009-02-02

Applicant: 삼성전자주식회사

Inventor： 장종광 ,  이화성 ,  김명선 ,  신홍재 ,  이내인

IPC: H01L21/336 ,  H01L29/78

CPC classification number: H01L29/0847 ,  H01L29/66636 ,  H01L29/7834 ,  H01L29/7848 ,  H01L21/02293

Abstract: PURPOSE: A semiconductor device and a method for manufacturing the same are provided to maintain a stress which applied to the channel region of a gate structure by forming a trench which includes regions with different depths. CONSTITUTION: A first gate structure(120a) and a second gate structure(120b) are spaced apart on a substrate(100). A source/drain region(110) is formed on both sides of the first and the second gate structures. A trench(130) is formed between the first and the second gate structures. An epitaxial layer(140) fills the trench. A first gate insulating layer(121a) and a second gate insulating layer(121b) electrically insulates the substrate, a first gate electrode(122a), and a second gate electrode(122b). A first sidewall spacer(123a) and a second sidewall spacer(123b) are composed of an insulating material.

Abstract translation: 目的：提供半导体器件及其制造方法，以通过形成包括具有不同深度的区域的沟槽来保持施加到栅极结构的沟道区的应力。 构成：第一栅极结构（120a）和第二栅极结构（120b）在衬底（100）上间隔开。 源极/漏极区域（110）形成在第一和第二栅极结构的两侧。 在第一和第二栅极结构之间形成沟槽（130）。 外延层（140）填充沟槽。 第一栅极绝缘层（121a）和第二栅极绝缘层（121b）使基板，第一栅电极（122a）和第二栅电极（122b）电绝缘。 第一侧壁间隔物（123a）和第二侧壁间隔物（123b）由绝缘材料构成。

公开(公告)号：KR1020100061034A

公开(公告)日：2010-06-07

申请号：KR1020080119907

申请日：2008-11-28

Applicant: 삼성전자주식회사

Inventor： 장종광 ,  신홍재 ,  이내인 ,  백광현 ,  복승일 ,  김효정

IPC: H01L21/308 ,  H01L21/027

CPC classification number: H01L21/0337 ,  H01L21/0338

Abstract: PURPOSE: A fabricating method of semiconductor integrated circuit devices are provided to form a spacer layer on a hard mask pattern with conformal by forming a line spacer with a low temperature oxide film. CONSTITUTION: A hard mask layer is formed on a semiconductor substrate(100). A first etching mask including a plurality of first line patterns is formed on the hard mask layer. The hard mask layer is etched and the first hard mask pattern is formed. A second etching mask including a plurality of second line patterns is formed in the first hard mask pattern. The first hard mask pattern is etched to form the second hard mask pattern(122). The spacer(131) is formed in the sidewall of the second hard mask pattern.

Abstract translation: 目的：提供半导体集成电路器件的制造方法，通过形成具有低温氧化膜的线间隔物，在硬掩模图案上形成间隔层。 构成：在半导体衬底（100）上形成硬掩模层。 在硬掩模层上形成包括多个第一线图案的第一蚀刻掩模。 蚀刻硬掩模层并形成第一硬掩模图案。 在第一硬掩模图案中形成包括多个第二线图案的第二蚀刻掩模。 蚀刻第一硬掩模图案以形成第二硬掩模图案（122）。 间隔物（131）形成在第二硬掩模图案的侧壁中。

公开(公告)号：KR1020090059850A

公开(公告)日：2009-06-11

申请号：KR1020070126911

申请日：2007-12-07

Applicant: 삼성전자주식회사

Inventor： 문창욱 ,  양현덕 ,  전중석 ,  이화성 ,  이내인 ,  첸웨이웨이

IPC: H01L21/24 ,  H01L29/78

CPC classification number: H01L29/7848 ,  H01L21/28518 ,  H01L29/165 ,  H01L29/66636 ,  H01L29/78 ,  H01L29/665

Abstract: A method for forming a Ge silicide layer, a semiconductor device including a Ge silicide layer, and a manufacturing method thereof are provided to prevent degradation of a silicon germanium layer by using a laser spike annealing. An isolation film(5) limits an active region in a substrate(1). The substrate has a source region(100a) and a drain region(100b). A gate(200) is included on the substrate between the source region and the drain region. An insulation spacer(210) is included in both side walls of the gate. A first Ge silicide layer(300a) and a second Ge silicide layer(300b) are included on the source region and the drain region. An interlayer dielectric(400) is included on the substrate. The interlayer dielectric has a first contact hole(H1) and a second contact hole(H2). A first conductive plug(500a) and a second conductive plug(500b) are included inside the first contact hole and the second contact hole.

Abstract translation: 提供一种形成锗硅化物层的方法，包括锗硅化物层的半导体器件及其制造方法，以通过使用激光尖峰退火来防止硅锗层的劣化。 隔离膜（5）限制衬底（1）中的有源区。 衬底具有源区（100a）和漏区（100b）。 在源极区域和漏极区域之间的衬底上包括栅极（200）。 绝缘垫片（210）包括在门的两个侧壁中。 第一锗硅化物层（300a）和第二锗硅化物层（300b）包括在源极区域和漏极区域上。 衬底上包含层间电介质（400）。 层间电介质具有第一接触孔（H1）和第二接触孔（H2）。 第一导电插头（500a）和第二导电插头（500b）包括在第一接触孔和第二接触孔内。

公开(公告)号：KR100772902B1

公开(公告)日：2007-11-05

申请号：KR1020060095117

申请日：2006-09-28

Applicant: 삼성전자주식회사

Inventor： 남서우 ,  김기철 ,  추재욱 ,  문영준 ,  신홍재 ,  이내인

IPC: H01L29/78

CPC classification number: H01L21/823412 ,  H01L21/823807 ,  H01L27/088 ,  H01L27/092 ,  H01L29/665 ,  H01L29/6659 ,  H01L29/7843 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor device and a manufacturing method thereof are provided to improve a contact property of the semiconductor device by partially or globally removing a second stress film from an overlap region between the first and the second stress films. A semiconductor substrate(100) includes first and second transistor regions and a border region. The first transistor region includes a first gate electrode and a first source/drain region. The second transistor region includes a second gate electrode and a second source/drain region. The border region includes a third gate electrode and is arranged on an interface between the first and the second transistor regions. A first stress film(131) covers the first gate and the first source/drain region and at least a portion of the third generates. A second stress film(135) covers the second gate and the second source/drain region and is not overlapped with the first stress film or partially overlapped with the first stress film. A thickness of the partially overlapped second stress film is smaller than that of the second stress film on the second transistor region.

Abstract translation: 提供半导体器件及其制造方法，以通过从第一和第二应力膜之间的重叠区域部分地或全局地去除第二应力膜来改善半导体器件的接触特性。 半导体衬底（100）包括第一和第二晶体管区域和边界区域。 第一晶体管区域包括第一栅极电极和第一源极/漏极区域。 第二晶体管区域包括第二栅极电极和第二源极/漏极区域。 边界区域包括第三栅电极，并且布置在第一和第二晶体管区域之间的界面上。 第一应力膜（131）覆盖第一栅极和第一源极/漏极区域，并且第三应力膜片的至少一部分产生。 第二应力膜（135）覆盖第二栅极和第二源极/漏极区域，并且不与第一应力膜重叠或部分地与第一应力膜重叠。 部分重叠的第二应力膜的厚度小于第二晶体管区域上的第二应力膜的厚度。

公开(公告)号：KR100532429B1

公开(公告)日：2005-11-30

申请号：KR1020030024779

申请日：2003-04-18

Applicant: 삼성전자주식회사

Inventor： 김성호 ,  이내인 ,  고광욱 ,  배금종 ,  김기철 ,  김진희 ,  조인욱 ,  김상수

IPC: G11C17/12

CPC classification number: H01L27/11568 ,  G11C16/0416 ,  G11C16/0466 ,  H01L21/28273 ,  H01L21/28282 ,  H01L27/0207 ,  H01L27/115 ,  H01L27/11519 ,  H01L27/11521 ,  H01L27/11524 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/792

Abstract: 바이트 단위로 저장된 정보를 일괄 소거할 수 있는 바이트 오퍼레이션 비휘발성 반도체 메모리 장치에 대하여 개시한다. 본 발명의 일 실시예에 의한 반도체 메모리 장치에 의하면, 메모리 셀 어레이를 구성하는 바이트 메모리 셀은, 일 방향으로 길게 배열되어 액티브 영역에 각각의 정션 영역 및 채널 영역이 형성되어 있는 1바이트 메모리 트랜지스트와 액티브 영역에 형성되어 있고, 정션 영역이 1바이트 메모리 트랜바이트 각각의 정션 영역과 직접 연결되어 있는 바이트 선택 트랜지스터를 포함한다. 그리고, 바이트 선택 트랜지스터는 1바이트 메모리 트랜지스터가 배열되어 있는 방향에 수직한 방향으로 상부 또는 하부에 위치한다.

公开(公告)号：KR100464861B1

公开(公告)日：2005-01-06

申请号：KR1020030011309

申请日：2003-02-24

Applicant: 삼성전자주식회사

Inventor： 조인욱 ,  이내인 ,  고광욱 ,  배금종 ,  김상수 ,  김진희 ,  김성호 ,  김기철

IPC: H01L27/115

CPC classification number: H01L27/115 ,  H01L27/11568 ,  Y10S438/954

Abstract: A method of manufacturing a non-volatile semiconductor memory device begins by forming a dielectric layer pattern having an ONO composition on a substrate. A polysilicon layer is formed on the substrate including over the dielectric layer pattern. The polysilicon layer is patterned to form a split polysilicon layer pattern that exposes part of the dielectric layer pattern. The exposed dielectric layer is etched, and then impurities are implanted into portions of the substrate using the split polysilicon layer pattern as a mask to thereby form a source region having a vertical profile in the substrate.

Abstract translation: 制造非易失性半导体存储器件的方法开始于在衬底上形成具有ONO成分的介电层图案。 在包括介电层图案上的衬底上形成多晶硅层。 多晶硅层被图案化以形成暴露部分介电层图案的分裂多晶硅层图案。 蚀刻暴露的电介质层，然后使用分离的多晶硅层图案作为掩模将杂质注入到衬底的部分中，从而在衬底中形成具有垂直轮廓的源极区。

公开(公告)号：KR1020040082019A

公开(公告)日：2004-09-23

申请号：KR1020030052088

申请日：2003-07-28

Applicant: 삼성전자주식회사

Inventor： 배금종 ,  이내인 ,  고광욱 ,  김기철 ,  김상수 ,  김진희 ,  김성호 ,  조인욱

IPC: H01L27/115

CPC classification number: H01L29/792 ,  H01L29/7923 ,  Y10S438/954

Abstract: PURPOSE: A local SONOS(Silicon-Oxide-Nitride-Oxide-Silicon) structure having two-piece gates and a self-aligned ONO(Oxide-Nitride-Oxide) and a fabricating method thereof are provided to stabilize each threshold voltage characteristic of a programmed cell and an erased cell by forming simultaneously an ONO structure and the first gate layer as a control gate. CONSTITUTION: An ONO structure(1030) is formed on an upper surface of a substrate(1002). The first gate layer is formed on an upper surface of the ONO structure. A gate insulating layer(1023) is arranged beside the ONO structure on the substrate. The second gate layer is formed on the first gate layer and the gate insulating layer and is electrically connected to the first gate layer. A local SONOS structure of one or more bits is defined by the ONO structure, the first gate layer, and the second gate layer.

Abstract translation: 目的：提供具有双片栅极和自对准ONO（氧化氮化物 - 氧化物）的本地SONOS（硅氧化物 - 氮化物 - 氧化物 - 硅）结构及其制造方法，以稳定每个阈值电压特性 通过同时形成ONO结构和将第一栅极层作为控制栅极而形成擦除单元。 构成：在衬底（1002）的上表面上形成ONO结构（1030）。 第一栅极层形成在ONO结构的上表面上。 栅极绝缘层（1023）布置在基板上的ONO结构的旁边。 第二栅极层形成在第一栅极层和栅极绝缘层上，并与第一栅极层电连接。 一个或多个位的本地SONOS结构由ONO结构，第一栅极层和第二栅极层限定。