公开(公告)号：KR100407693B1

公开(公告)日：2003-11-28

申请号：KR1020010039998

申请日：2001-07-05

Applicant: 한국전자통신연구원

Inventor： 유현규 ,  한선호 ,  박문양 ,  김성도 ,  윤용식 ,  김이섭 ,  성기혁 ,  양병도 ,  김영준

IPC: H03B28/00

CPC classification number: G06F1/0356 ,  G06F1/0328 ,  G06F2101/04 ,  G11C17/00

Abstract: The present invention relates to a ROM division method for reducing the size of a ROM in a direct digital frequency synthesizer (DDFS), which is used to synthesize a frequency in a communication system requiring fast frequency conversion. A ROM consuming most energy in the system, a modified Nicholas architecture is brought forth to reduce the size of ROM. In this modified Nicholas architecture, a ROM is divided into coarse ROM and fine ROM to convert phase to sine value. The present invention divides the coarse ROM and the fine ROM into quantized ROM and error ROM respectively. Then, value stored in each ROM is segmented in certain intervals and the minimum quantized value in each of the section is stored in the quantized ROM, while the difference between the original ROM value and the quantized ROM value is stored in the error ROM. This way, the size of a ROM can be reduced. Phase value inputted in a DDFS, a sine value is calculated by adding the four ROM values, i.e., coarse-quantized ROM, coarse-error ROM, fine-quantized ROM and fine-error ROM.

Abstract translation: 本发明涉及一种用于减小直接数字频率合成器（DDFS）中的ROM的尺寸的ROM分割方法，其用于在需要快速频率转换的通信系统中合成频率。 在系统中消耗大部分能量的ROM，提出了一种改进的Nicholas架构来减小ROM的尺寸。 在这种改进的Nicholas架构中，ROM分为粗略ROM和精细ROM，以将相位转换为正弦值。 本发明分别将粗略ROM和精细ROM分成量化ROM和错误ROM。 然后，存储在每个ROM中的值以一定的间隔被分段，并且每个段中的最小量化值被存储在量化ROM中，而原始ROM值和量化ROM值之间的差被存储在错误ROM中。 这样可以减少ROM的大小。 在DDFS中输入的相位值，正弦值是通过加上四个ROM值即粗量化ROM，粗误ROM，精量量ROM和微误差ROM来计算的。

公开(公告)号：KR1020030013194A

公开(公告)日：2003-02-14

申请号：KR1020010047550

申请日：2001-08-07

Applicant: 한국전자통신연구원

Inventor： 유현규 ,  한선호 ,  박문양 ,  김성도 ,  윤용식 ,  김이섭 ,  양병도 ,  성기혁

IPC: G11C17/00

Abstract: PURPOSE: A low-power ROM is provided to be capable of reducing an area while lowering power consumption at a read operation. CONSTITUTION: Column selection transistors(Ms1-Msn) select one of a plurality of bit lines. A common connection terminal is connected in common to one ends of the column selection transistors, and precharges the bit lines with a charge sharing voltage when the column selection transistors are turned on. A precharge part(Mp1) precharges the common connection terminal with a power supply voltage(VCC). A reference voltage generating part is connected to the precharge part, and generates a reference voltage used to compare voltages of the bit lines. A sense amplifier(SA) receives the reference voltage and a charge sharing voltage of the common connection terminal.

Abstract translation: 目的：提供低功耗ROM，以便在读取操作时降低功耗，从而减少面积。 构成：列选择晶体管（Ms1-Msn）选择多个位线之一。 公共连接端子共同连接到列选择晶体管的一端，并且当列选择晶体管导通时，利用电荷共享电压对位线进行预充电。 预充电部分（Mp1）用公共连接端子对电源电压（VCC）进行预充电。 参考电压产生部分连接到预充电部分，并且产生用于比较位线的电压的参考电压。 读出放大器（SA）接收公共连接端子的参考电压和电荷共享电压。