公开(公告)号：KR1020030004496A

公开(公告)日：2003-01-15

申请号：KR1020010039998

申请日：2001-07-05

Applicant: 한국전자통신연구원

Inventor： 유현규 ,  한선호 ,  박문양 ,  김성도 ,  윤용식 ,  김이섭 ,  성기혁 ,  양병도 ,  김영준

IPC: H03B28/00

CPC classification number: G06F1/0356 ,  G06F1/0328 ,  G06F2101/04 ,  G11C17/00

Abstract: PURPOSE: A ROM driving method and a digital frequency synthesizer(DDFS) using the same are provided to reduce a power consumption and a size by minimizing a size of a ROM in a digital frequency synthesizer. CONSTITUTION: When an original ROM has 2k input addresses and 2i sections, "i" is initialized as "k"(S31). A variable "q" is initialized as an output bit number of the original ROM(S32). A smallest one among q bit values is stored in a quantization ROM(S33). A difference of quantization values stored in the quantization ROM is obtained(S34). A bit number "e" bit is searched in order to store the greatest error among errors in all input addresses(S35). A total ROM size is calculated(S36). A "q" is reduced by "1" until it becomes "1"(S37). A "i" is reduced by "1" until it becomes "1"(S38). "i, q, and e" values having the smallest ROM size are searched(S39).

Abstract translation: 目的：提供使用其的ROM驱动方法和数字频率合成器（DDFS），以通过使数字频率合成器中的ROM的尺寸最小化来降低功耗和尺寸。 构成：当原始ROM具有2k个输入地址和2i个区段时，“i”被初始化为“k”（S31）。 变量“q”被初始化为原始ROM的输出位数（S32）。 q位值中的最小值存储在量化ROM中（S33）。 获得存储在量化ROM中的量化值的差异（S34）。 搜索位数“e”，以便在所有输入地址中存储错误中的最大误差（S35）。 计算总ROM大小（S36）。 A“q”减小到“1”（S37）。 A“i”减少到“1”（S38）。 搜索具有最小ROM大小的“i，q和e”值（S39）。

公开(公告)号：KR100424676B1

公开(公告)日：2004-03-27

申请号：KR1020010047550

申请日：2001-08-07

Applicant: 한국전자통신연구원

Inventor： 유현규 ,  한선호 ,  박문양 ,  김성도 ,  윤용식 ,  김이섭 ,  양병도 ,  성기혁

IPC: G11C17/00

Abstract: PURPOSE: A low-power ROM is provided to be capable of reducing an area while lowering power consumption at a read operation. CONSTITUTION: Column selection transistors(Ms1-Msn) select one of a plurality of bit lines. A common connection terminal is connected in common to one ends of the column selection transistors, and precharges the bit lines with a charge sharing voltage when the column selection transistors are turned on. A precharge part(Mp1) precharges the common connection terminal with a power supply voltage(VCC). A reference voltage generating part is connected to the precharge part, and generates a reference voltage used to compare voltages of the bit lines. A sense amplifier(SA) receives the reference voltage and a charge sharing voltage of the common connection terminal.

Abstract translation: 目的：提供低功率ROM，以便在读取操作时降低功耗并减小面积。 构成：列选择晶体管（Ms1-Msn）选择多个位线中的一个。 公共连接端子共同连接到列选择晶体管的一端，并且当列选择晶体管导通时利用电荷共享电压预充电位线。 预充电部分（Mp1）利用电源电压（VCC）预充电公共连接端子。 参考电压生成部件连接到预充电部件，并且生成用于比较位线的电压的参考电压。 读出放大器（SA）接收公共连接端子的参考电压和电荷共享电压。

公开(公告)号：KR100407693B1

公开(公告)日：2003-11-28

申请号：KR1020010039998

申请日：2001-07-05

Applicant: 한국전자통신연구원

Inventor： 유현규 ,  한선호 ,  박문양 ,  김성도 ,  윤용식 ,  김이섭 ,  성기혁 ,  양병도 ,  김영준

IPC: H03B28/00

CPC classification number: G06F1/0356 ,  G06F1/0328 ,  G06F2101/04 ,  G11C17/00

Abstract: The present invention relates to a ROM division method for reducing the size of a ROM in a direct digital frequency synthesizer (DDFS), which is used to synthesize a frequency in a communication system requiring fast frequency conversion. A ROM consuming most energy in the system, a modified Nicholas architecture is brought forth to reduce the size of ROM. In this modified Nicholas architecture, a ROM is divided into coarse ROM and fine ROM to convert phase to sine value. The present invention divides the coarse ROM and the fine ROM into quantized ROM and error ROM respectively. Then, value stored in each ROM is segmented in certain intervals and the minimum quantized value in each of the section is stored in the quantized ROM, while the difference between the original ROM value and the quantized ROM value is stored in the error ROM. This way, the size of a ROM can be reduced. Phase value inputted in a DDFS, a sine value is calculated by adding the four ROM values, i.e., coarse-quantized ROM, coarse-error ROM, fine-quantized ROM and fine-error ROM.

Abstract translation: 本发明涉及一种用于减小直接数字频率合成器（DDFS）中的ROM的尺寸的ROM分割方法，其用于在需要快速频率转换的通信系统中合成频率。 在系统中消耗大部分能量的ROM，提出了一种改进的Nicholas架构来减小ROM的尺寸。 在这种改进的Nicholas架构中，ROM分为粗略ROM和精细ROM，以将相位转换为正弦值。 本发明分别将粗略ROM和精细ROM分成量化ROM和错误ROM。 然后，存储在每个ROM中的值以一定的间隔被分段，并且每个段中的最小量化值被存储在量化ROM中，而原始ROM值和量化ROM值之间的差被存储在错误ROM中。 这样可以减少ROM的大小。 在DDFS中输入的相位值，正弦值是通过加上四个ROM值即粗量化ROM，粗误ROM，精量量ROM和微误差ROM来计算的。

公开(公告)号：KR1020030013194A

公开(公告)日：2003-02-14

申请号：KR1020010047550

申请日：2001-08-07

Applicant: 한국전자통신연구원

Inventor： 유현규 ,  한선호 ,  박문양 ,  김성도 ,  윤용식 ,  김이섭 ,  양병도 ,  성기혁

IPC: G11C17/00

Abstract: PURPOSE: A low-power ROM is provided to be capable of reducing an area while lowering power consumption at a read operation. CONSTITUTION: Column selection transistors(Ms1-Msn) select one of a plurality of bit lines. A common connection terminal is connected in common to one ends of the column selection transistors, and precharges the bit lines with a charge sharing voltage when the column selection transistors are turned on. A precharge part(Mp1) precharges the common connection terminal with a power supply voltage(VCC). A reference voltage generating part is connected to the precharge part, and generates a reference voltage used to compare voltages of the bit lines. A sense amplifier(SA) receives the reference voltage and a charge sharing voltage of the common connection terminal.

Abstract translation: 目的：提供低功耗ROM，以便在读取操作时降低功耗，从而减少面积。 构成：列选择晶体管（Ms1-Msn）选择多个位线之一。 公共连接端子共同连接到列选择晶体管的一端，并且当列选择晶体管导通时，利用电荷共享电压对位线进行预充电。 预充电部分（Mp1）用公共连接端子对电源电压（VCC）进行预充电。 参考电压产生部分连接到预充电部分，并且产生用于比较位线的电压的参考电压。 读出放大器（SA）接收公共连接端子的参考电压和电荷共享电压。