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公开(公告)号：KR1019920010970B1
公开(公告)日：1992-12-26
申请号：KR1019900021863
申请日：1990-12-26
Applicant: 한국전자통신연구원
IPC: G06F12/08
Abstract: The circuit generates the control signal that represents the state of the data block stored in a cache memory with high speed to improve the efficiency of bus usage. It includes an electrically programmable memory (EPM) for receiving write-backing signal (WBING), parity error signal of bus (BPERR), acting signal (ACT), time pulse (TP), bus address deciding signal (BA-SELF), tag-match signal (TG-MATCH) etc. froma controller, outputting one of the control signals (SHARED,SNACK,DIRTY) through one of I/O12, I/O13 and I/O14, and driving bus control signals (BUS-SHARED, BUS- SNACK, BUS-DIRTY) to be zero through NAND gates (N1,N2,N3).
Abstract translation: 电路以高速生成表示存储在高速缓冲存储器中的数据块的状态的控制信号，以提高总线使用的效率。 它包括用于接收写背信号（WBING），总线奇偶校验错误信号（BPERR），作用信号（ACT），时间脉冲（TP），总线地址决定信号（BA-SELF）等）的电可编程存储器（EPM） 标签匹配信号（TG-MATCH）等，通过I / O12，I / O13和I / O14之一输出控制信号（SHARED，SNACK，DIRTY）之一，以及驱动总线控制信号（BUS- 共享，BUS-SNACK，BUS-DIRTY）通过NAND门（N1，N2，N3）为零。
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Patent Agency Ranking
公开(公告)号：KR1019920009453B1
公开(公告)日：1992-10-16
申请号：KR1019900021869
申请日：1990-12-26
Applicant: 한국전자통신연구원
IPC: G06F13/38
Abstract: The information searcher for the bus state analyzer can vary and define the quantity of the information searched and the condition of trigger. The searcher comprises basic unit modules (1-1n) for searching informations, and an integrating section (2) for integrating and multiplying logically the results of searched from the modules (1-1n), and generating the results.
Abstract translation: 总线状态分析器的信息搜索器可以变化并定义所搜索的信息的数量和触发条件。 搜索器包括用于搜索信息的基本单元模块（1-1n）和用于在逻辑上对从模块（1-1n）搜索的结果进行积分和乘积的积分部分（2），并且生成结果。
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公开(公告)号：KR1019920007945B1
公开(公告)日：1992-09-19
申请号：KR1019890019676
申请日：1989-12-27
Applicant: 한국전자통신연구원
IPC: G06F12/00
Abstract: The slot address designating method is to designating positions for slots of each system bus exclusively so that the processor boards inserted to the slots detects the position to which the boards are inserted. The position data for each processor board are assigned to signal pins of system bus (3) and the address designation or the interleaving sequence control is executed with priority.
Abstract translation: 插槽地址指定方法是专门为每个系统总线的时隙指定位置，以便插入插槽的处理器板检测插入板的位置。 每个处理器板的位置数据被分配给系统总线（3）的信号引脚，优先执行地址指定或交织序列控制。
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