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公开(公告)号：KR1019940010925B1
公开(公告)日：1994-11-19
申请号：KR1019910024257
申请日：1991-12-24
Applicant: 한국전자통신연구원
IPC: H01L29/772
Abstract: The method includes the steps of implanting high concentration Si ions into a substrate (4) to define a drain region to form a P type ion implantation region and an insulating film (1), inclined-etching the film (1), drain region, P type region and substrate (4) by using a resist pattern (5) to implant Si ions into the etched substrate to form a source region (6), implanting high concentration Si ions into the tilted substrate to form a channel between the source and drain regions, depositing an insulating layer (8), for isolating between the source and gate, on the source (6) and film (1), inclined-depositing a metallic layer thereon to form a gate for controlling the current of the channel layer, and depositing and thermal-treating an ohmic metallic layer on the source and drain regions, thereby defining the gate length with the etching and metal deposition processes regardless of the lithography process.
Abstract translation: 该方法包括以下步骤：将高浓度Si离子注入到衬底（4）中以限定形成P型离子注入区的漏极区和绝缘膜（1），将膜（1），漏区， P型区域和衬底（4），通过使用抗蚀剂图案（5）将Si离子注入蚀刻的衬底中以形成源极区域（6），将高浓度Si离子注入到倾斜衬底中以在源极和 漏极区域，在源极（6）和膜（1）上沉积用于在源极和栅极之间隔离的绝缘层（8），在其上倾斜沉积金属层以形成用于控制沟道层电流的栅极 ，并且在源极和漏极区域上沉积和热处理欧姆金属层，从而与蚀刻和金属沉积工艺限定栅极长度，而与光刻工艺无关。
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公开(公告)号：KR1019940007668B1
公开(公告)日：1994-08-22
申请号：KR1019910024510
申请日：1991-12-26
Applicant: 한국전자통신연구원
IPC: H01L29/78
CPC classification number: H01L29/66871 , H01L21/2258 , H01L21/2654 , H01L21/26553 , H01L21/2656
Abstract: The method improves electrical characterisics of a GaAs MESFET by doping silicon on an ohmic contact area and recess etching an electrode area. The method comprises (A) vaporing a silicon layer (202) on a substrate (201); (B) injecting ion on a substrate to form an active region (204); (C) forming an ohmic electrode contact region and injecting ion on an active region (204); (D) forming a protective layer (206) on the whole surface of a substrate (201) and heating to diffuse silicon on a silicon layer (202) and a silicon layer (202); (F) recess etching a substrate using a third photosensitive layer and forming an ohmic electrode (208) on an etched region; and (G) forming a gate (209) by recess etching process.
Abstract translation: 该方法通过在欧姆接触区域上掺杂硅并且凹陷蚀刻电极区域来改善GaAs MESFET的电特性。 该方法包括：（A）在衬底（201）上蒸发硅层（202）; （B）在衬底上注入离子以形成有源区（204）; （C）形成欧姆电极接触区域并在有源区域（204）上注入离子; （D）在基板（201）的整个表面上形成保护层（206）并加热以在硅层（202）和硅层（202）上扩散硅; （F）使用第三感光层来蚀刻衬底并在蚀刻区域上形成欧姆电极（208）; 和（G）通过凹陷蚀刻工艺形成栅极（209）。
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公开(公告)号：KR1019940001236B1
公开(公告)日：1994-02-18
申请号：KR1019910012522
申请日：1991-07-22
Applicant: 한국전자통신연구원
IPC: G11B7/00
Abstract: The method arrays a noncrystalized chalcogenide (7) by a constant polarized recording light (8) and for recording the data to the desired location by a lineary polarized recording light (9). The device includes a reading light source (11), a lens (12) for converting the linearly polarized light (10) into the paralleling light, a polarizing beam splitter (15) for reflecting the paralleling light, a quater wave retardation plate (14) for passing the light, a light converging lens (15), an optic recording device (16) for recording the light information, and a photo detector (17) for deciding the axis of light degrees (450).
Abstract translation: 该方法通过恒定的偏振记录光（8）排列非结晶的硫族化物（7），并通过线偏振记录光（9）将数据记录到期望的位置。 该装置包括读取光源（11），用于将线偏振光（10）转换成并列光的透镜（12），用于反射并联光的偏振分束器（15），四分之一波长相位差板（14） ），聚光透镜（15），用于记录光信息的光记录装置（16），以及用于决定光度轴（450）的光检测器（17）。
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Patent Agency Ranking
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公开(公告)号：KR1019920005128B1
公开(公告)日：1992-06-26
申请号：KR1019890019572
申请日：1989-12-27
Applicant: 한국전자통신연구원
IPC: H01L29/73
CPC classification number: H01L29/66462 , H01L21/28587 , Y10S438/944
Abstract: 내용 없음.
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