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11.发明公开복수의 컴퓨터와 복수의 터미널 간 상호 연결을 지원하는 전자 교환기, 전자 교환 시스템 및 전자 교환 시스템의 제어 방법 有权用于支持多个计算机与多个终端之间的互连的电子交换机，其系统及其控制方法
公开(公告)号：KR1020110001205A
公开(公告)日：2011-01-06
申请号：KR1020090058617
申请日：2009-06-29
Applicant: 한국전자통신연구원
CPC classification number: H04L12/46
Abstract: PURPOSE: An electronic switching system for simplifying maintenance and repair of a computer is provided to dynamically use the computer under a cloud computing environment and a utility computing environment. CONSTITUTION: A computer group includes a plurality of computers. A terminal group includes a plurality of terminal. An electronic exchanger(100) dynamically interlinks each computer of the computer group and each terminal of the terminal group. Switching devices connect or disconnect the terminal with the computer according to updated information of a control unit.
Abstract translation: 目的：提供一种用于简化计算机维护和维修的电子交换系统，以便在云计算环境和实用计算环境下动态使用计算机。 构成：计算机组包括多台计算机。 终端组包括多个终端。 电子交换机（100）动态地互连计算机组的每个计算机和终端组的每个终端。 交换设备根据控制单元的更新信息，将终端与计算机连接或断开连接。
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公开(公告)号：KR1020100064442A
公开(公告)日：2010-06-15
申请号：KR1020080122876
申请日：2008-12-05
Applicant: 한국전자통신연구원
CPC classification number: G06F13/4217 , Y02D10/14 , Y02D10/151
Abstract: PURPOSE: An encoding method of a bus signal, and a decoding method and a device thereof are provided to perform a serial signal of a parallel microprocessor bus and reduce signal fluctuation of the bus signal thereby preventing increase of power consumption according to the signal fluctuation. CONSTITUTION: If a parallel bus signal is received, an encoder performs an XOR operation of the other byte sequences except the first byte sequence of a bus signal through am XOR operator by a bit unit(S301,S302). The encoder performs inverting of even-numbered byte sequences by a bit unit(S303). The encoder encodes the bus signal by serialization of the inverted bus signal(S304). The encoder transmits a serialized bus signal to a receiving device(S305).
Abstract translation: 目的：提供总线信号的编码方法及其解码方法及其装置，以执行并行微处理器总线的串行信号，并减少总线信号的信号波动，从而防止根据信号波动的功耗的增加。 构成：如果接收到并行总线信号，编码器通过一个位单元（S301，S302）通过异或运算器执行除总线信号的第一个字节序列之外的其他字节序列的异或运算。 编码器通过位单位执行偶数字节序列的反相（S303）。 编码器通过反相总线信号的串行化对总线信号进行编码（S304）。 编码器将串行总线信号发送到接收装置（S305）。
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公开(公告)号：KR100498233B1
公开(公告)日：2005-07-01
申请号：KR1020020066844
申请日：2002-10-31
Applicant: 한국전자통신연구원
IPC: G11C7/00
CPC classification number: G11C8/04
Abstract: 본원발명은 저속의 복수개 메모리를 이용하여 고속의 선입선출 동작을 수행하는 선입선출 메모리 회로는 표준 라이브러리 메모리를 이용한 선입선출 메모리 회로에 관한 것으로, N(N>1) 개의 동기식 듀얼 포트 메모리들로 구성된 메모리 블록과, N 개의 동기식 듀얼 포트 메모리들의 읽기 어드레스를 지정하는 단일 읽기 포인터와, N 개의 메모리들의 쓰기 어드레스를 지정하는 단일 쓰기 포인터와, 읽기/쓰기 어드레스에 따라 N 개의 메모리들 중에서 어느 하나의 메모리를 선택하고, 소스 클럭 신호를 n(n=N, n>1) 분주된 n 개의 읽기/쓰기 클럭 신호로 생성하며, 1/n 주기 차이를 갖는 n 개의 읽기/쓰기 클럭 신호를 상기 선택된 메모리부터 해당 메모리에 직접 분배하여 데이터를 입출력시키는 메모리 제어부를 포함한다.
이와 같이, 본 발명은 주문형 반도체 설계에 있어서 표준 라이브러리(standard cell library)를 이용하여 생성된 저속 메모리로 고속의 선입선출 메모리 구성이 가능하므로, 메모리와 일반 로직 회로의 속도 격차에 따른 선입선출 메모리의 비효율성을 제거하고, 간단하면서도 효율적인 제어회로를 통하여 설계시간의 단축과 공정/설계 변경에 따른 설계 비용을 최소화 할 수 있다.-
Patent Agency Ranking
公开(公告)号：KR1020040041712A
公开(公告)日：2004-05-20
申请号：KR1020020069556
申请日：2002-11-11
Applicant: 한국전자통신연구원
CPC classification number: H04L1/0061 , H04L1/0045 , H04L49/90 , H04L49/9063
Abstract: PURPOSE: A data packet receiving apparatus and a method thereof are provided to utilize a network communication and bandwidth of an input/output channel to the maximum by smoothly processing high speed packet stream. CONSTITUTION: An inspection logic circuit and a multiplexer receive packet data word(S801). The multiplexer transfers the packet data word to input/output memory units and the inspection logic circuit analyzes the packet data word(S802). Upon analyzing the packet data word, if the packet data word is a header part, the inspection logic circuit performs a packet header processing process, if the packet data word is a data part, the inspection logic circuit performs a packet data and error correction code calculating process, and if it is an end part, the inspection logic circuit compares the calculated error correction code and an error correction code of the end of the packet(S803). It is determined whether an error has been discovered by the inspection logic circuit, and if an error has been discovered, the packet is discarded(S804). If no error has been discovered, an upper processing layer processes packet data words outputted from the input/output memory units(S805). The upper processing layer determines whether an error is discovered(S806). If an error is discovered, the packet is discarded(S807).
Abstract translation: 目的：提供一种数据分组接收装置及其方法，通过平滑处理高速分组流，最大限度地利用输入/输出信道的网络通信和带宽。 构成：检查逻辑电路和复用器接收分组数据字（S801）。 复用器将分组数据字传送到输入/输出存储单元，检查逻辑电路分析分组数据字（S802）。 分析分组数据字时，如果分组数据字是报头部分，则检查逻辑电路执行分组报头处理处理，如果分组数据字是数据部分，则检查逻辑电路执行分组数据和纠错码 计算处理，如果是结束部分，则检查逻辑电路将计算出的纠错码与分组结束的纠错码进行比较（S803）。 确定检查逻辑电路是否发现错误，如果发现错误，则丢弃该数据包（S804）。 如果没有发现错误，则上层处理层处理从输入/输出存储单元输出的分组数据字（S805）。 上层处理层确定是否发现错误（S806）。 如果发现错误，则丢弃该数据包（S807）。
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公开(公告)号：KR1020120063956A
公开(公告)日：2012-06-18
申请号：KR1020100125145
申请日：2010-12-08
Applicant: 한국전자통신연구원
IPC: G06F13/14
Abstract: PURPOSE: A multiuser pc system capable of providing pc utilization service to users from long distance is provided to enable users to connect to a PC main body using personal interface equipment using a standard LAN cable. CONSTITUTION: A multiuser pc system comprises the following: PC-side connection devices connected to a user interface on a PC main body; user-side connection devices providing the user interface to each user using a FTP(foiled twisted pair) or STP(shielded twisted pair) cable from long distance; and a connection management device(30) managing the connection among the PC-side and user-side connection devices, and monitoring the condition of the connection devices.
Abstract translation: 目的：提供能够从长距离为用户提供电脑使用服务的多用户电脑系统，使用户能够使用标准LAN电缆使用个人接口设备连接到PC主机。 构成：多用户电脑系统包括：连接PC主机用户界面的PC侧连接装置; 用户侧连接设备，使用FTP（双绞线双绞线）或STP（屏蔽双绞线）长距离向每个用户提供用户界面; 以及管理PC侧和用户侧连接装置之间的连接以及监视连接装置的状态的连接管理装置（30）。
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公开(公告)号：KR1020110057580A
公开(公告)日：2011-06-01
申请号：KR1020090114043
申请日：2009-11-24
Applicant: 한국전자통신연구원
Abstract: PURPOSE: An electronic switching system, computer resource distribution method, central control computer are provided to prevent the waste of hardware, software, and power consumption by connecting a high specification computer. CONSTITUTION: An interface unit(110) receives service information, which a user selects through a first terminal, from a first computer. A determining unit(120) supplies the service and searches for an available computer. An operation unit(130) operates an electronic switch and connects a second computer with the first terminal.
Abstract translation: 目的：提供电子交换系统，计算机资源分配方法，中央控制计算机，通过连接高规格计算机来防止硬件，软件和功耗的浪费。 构成：接口单元（110）从第一计算机接收用户通过第一终端选择的服务信息。 确定单元（120）提供服务并搜索可用的计算机。 操作单元（130）操作电子开关并将第二计算机与第一终端连接。
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公开(公告)号：KR1020100072794A
公开(公告)日：2010-07-01
申请号：KR1020080131305
申请日：2008-12-22
Applicant: 한국전자통신연구원
CPC classification number: G06F13/4217 , Y02D10/14 , Y02D10/151
Abstract: PURPOSE: A method for transmitting bus data and a device thereof are provided to minimize the amount of transmission data, thereby saving power consumption of a bus. CONSTITUTION: An aligner(126) configures previous byte by full byte which bit number is same as bit number of previous byte if upper bit of previous byte and upper bit of previous bit is same. The aligner configures the current byte by half byte which omitted the upper bit of the current byte. The aligner compresses a bus data by combination of full byte and half byte. The aligner arranges the compressed bus data to pre set bus band width.
Abstract translation: 目的：提供一种用于发送总线数据的方法及其装置，以最小化传输数据量，从而节省总线的功耗。 构成：如果前一个字节的高位和前一位的高位相同，则对齐器（126）将前一个字节配置为全字节，该位的数字与前一个字节的位数相同。 对齐器将当前字节配置为半字节，省略了当前字节的高位。 对齐器通过全字节和半字节的组合来压缩总线数据。 对准器将压缩的总线数据布置成预设的总线带宽。
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