公开(公告)号：DE60012639T2

公开(公告)日：2005-08-04

申请号：DE60012639

申请日：2000-03-02

Applicant: ALTERA CORP

Inventor： SCHLEICHER JAMES ,  PARK JIM ,  SHUMARAYEV SERGEY ,  PEDERSON BRUCE ,  NGAI TONY ,  HUANG WEI-JEN ,  MARURI VICTOR ,  PATEL RAKESH

IPC: G06F7/50 ,  G06F7/506 ,  H03K19/173 ,  H03K19/177

Abstract: A programmable logic device has many regions of programmable logic, together with relatively general-purpose, programmable, interconnection resources that can be used to make interconnections between virtually any of the logic regions. In addition, various types of more local interconnection resources are associated with each logic region for facilitating the making of interconnections between adjacent or nearby logic regions without the need to use the general-purpose interconnection resources for those interconnections. The local interconnection resources support flexible clustering of logic regions via relatively direct and therefore high-speed interconnections, preferably in both horizontal and vertical directions in the typically two-dimensional array of logic regions. The logic region clustering options provided by the local interconnection resources are preferably boundary-less or substantially boundary-less within the array of logic regions.

公开(公告)号：DE60012639D1

公开(公告)日：2004-09-09

申请号：DE60012639

申请日：2000-03-02

Applicant: ALTERA CORP

Inventor： SCHLEICHER JAMES ,  PARK JIM ,  SHUMARAYEV SERGEY ,  PEDERSON BRUCE ,  NGAI TONY ,  HUANG WEI-JEN ,  MARURI VICTOR ,  PATEL RAKESH

IPC: G06F7/50 ,  G06F7/506 ,  H03K19/173 ,  H03K19/177

Abstract: A programmable logic device has many regions of programmable logic, together with relatively general-purpose, programmable, interconnection resources that can be used to make interconnections between virtually any of the logic regions. In addition, various types of more local interconnection resources are associated with each logic region for facilitating the making of interconnections between adjacent or nearby logic regions without the need to use the general-purpose interconnection resources for those interconnections. The local interconnection resources support flexible clustering of logic regions via relatively direct and therefore high-speed interconnections, preferably in both horizontal and vertical directions in the typically two-dimensional array of logic regions. The logic region clustering options provided by the local interconnection resources are preferably boundary-less or substantially boundary-less within the array of logic regions.

公开(公告)号：GB2391671B

公开(公告)日：2004-04-28

申请号：GB0324461

申请日：2000-06-30

Applicant: ALTERA CORP

Inventor： NGAI TONY ,  SHUMARAYEV SERGEY ,  HUANG WEI-JEN ,  PATEL RAKESH H ,  LAI TIN

IPC: H03K19/177

公开(公告)号：JP2009065694A

公开(公告)日：2009-03-26

申请号：JP2008270378

申请日：2008-10-20

Applicant: Altera Corp ,  アルテラ コーポレイションAltera Corporation

Inventor： NGAI TONY ,  PEDERSEN BRUCE ,  SHUMARAYEV SERGEY ,  SCHLEICHER JAMES ,  HUANG WEI-JEN ,  HUTTON MICHAEL ,  MARURI VICTOR ,  PATEL RAKESH ,  KAZARIAN PETER J ,  LEAVER ANDREW ,  MENDEL DAVID W ,  PARK JIM

IPC: H03K19/173 ,  H01L21/82 ,  H03K19/177

CPC classification number: H03K19/17736 ,  H03K19/1737 ,  H03K19/17728 ,  H03K19/17744

Abstract: PROBLEM TO BE SOLVED: To provide interconnection resources applied to programmable logic devices for accelerating an operating speed of a programmable logic array integrated circuit device. SOLUTION: A programmable logic integrated circuit (10) has a plurality of regions of programmable logic (20) disposed on the device in a plurality of intersecting rows and columns of such regions. Interconnection resources (e.g., interconnection conductors, etc.) are provided for making programmable interconnections to, from and/or between the regions. At least some of these interconnection resources are provided in two forms having architecturally similar but significantly different signal propagation speed characteristics. For example, a major or larger portion of such dual-form interconnection resources (200a, 210a, 230a) may have what may be termed normal signal speed, while a smaller minor portion (200b, 210b, 230b) may have significantly faster signal speed. COPYRIGHT: (C)2009,JPO&INPIT

Abstract translation: 要解决的问题：提供应用于可编程逻辑器件的互连资源，以加速可编程逻辑阵列集成电路器件的工作速度。 解决方案：可编程逻辑集成电路（10）具有多个可编程逻辑区域（20），该多个可编程逻辑区域设置在该区域的多个相交行和列的多个设备上。 提供互连资源（例如，互连导体等），用于对区域之间和/或之间进行可编程互连。 这些互连资源中的至少一些以具有架构上相似但显着不同的信号传播速度特性的两种形式提供。 例如，这种双形互连资源（200a，210a，230a）的主要或更大部分可以具有所谓的正常信号速度，而较小次要部分（200b，210b，230b）可具有明显更快的信号速度 。 版权所有（C）2009，JPO＆INPIT

公开(公告)号：DE60129269D1

公开(公告)日：2007-08-23

申请号：DE60129269

申请日：2001-03-12

Applicant: ALTERA CORP A DELAWARE CORP

Inventor： NGAI TONY ,  PRASAD NITIN ,  TRAN THUNGOC

IPC: G11C8/16 ,  G11C7/10 ,  G11C8/00 ,  G11C11/00 ,  H03K19/177

Abstract: A programmable logic device includes, in addition to the usual regions of programmable logic and the programmable interconnect, at least one region of memory which has multiple independently usable write and/or read ports (e.g., two write ports and two read ports). Every memory cell in the memory region is accessible from any of these ports. This enables the memory region to be used to provide either one relatively large memory or two somewhat smaller memories, each occupying a fraction of the full memory. In the latter case, the two memories provided can have any of many different sizes relative to one another. Many different modes or combinations of modes of operating the memory region or parts of the memory region are possible.

公开(公告)号：GB2351824B

公开(公告)日：2004-03-31

申请号：GB0016223

申请日：2000-06-30

Applicant: ALTERA CORP

Inventor： NGAI TONY ,  SHUMARAYEV SERGEY ,  HUANG WEI-JEN ,  PATEL RAKESH H ,  LAI TIN

IPC: G11C5/02 ,  H03K19/177

Abstract: A high-performance programmable logic architecture has embedded memory (608). arranged at the peripheries or edges of the integrated circuit. This enhances the performance of the programmable logic integrated circuit by shortening the lengths of the programmable interconnect (748). In a specific embodiment, the memory blocks (703) are organized in rows along the top and bottom edges of the integrated circuit. The logic elements (805) can be directly programmable routed and connected to driver blocks (809) of the logic block in adjacent rows and columns. This permits fast interconnection of signals without using the global programmable interconnect resources (815, 825). Using similar direct programmable interconnections (828, 830, 835), the logic blocks can directly programmable connect to the memory blocks without using the global programmable interconnect resources. The present invention also provides technique of flexibly combining or stitching multiple memories together to form memories of a desired size.

公开(公告)号：JP2012044708A

公开(公告)日：2012-03-01

申请号：JP2011235492

申请日：2011-10-26

Applicant: Altera Corp ,  アルテラ コーポレイションAltera Corporation

Inventor： NGAI TONY ,  BRUCE PEDERSON ,  SERGEY SCHUMARAVE ,  SCHLEICHER JAMES ,  HUANG WEI-JEN ,  HUTTON MICHAEL ,  MARURI VICTOR ,  PATEL RAKESH ,  KAZARIAN PETER J ,  ANDREW LIEBER ,  MENDEL DAVID W ,  JIM PARK

IPC: H03K19/177 ,  H03K19/173

CPC classification number: H03K19/17736 ,  H03K19/1737 ,  H03K19/17728 ,  H03K19/17744

Abstract: PROBLEM TO BE SOLVED: To provide interconnection resources applied to programmable logic devices for accelerating an operating speed of a programmable logic array integrated circuit device.SOLUTION: A programmable logic integrated circuit (10) has a plurality of programmable logic regions (20) disposed on a device in an array of intersecting rows and columns of the plurality of regions. Interconnection resources (e.g., interconnection conductors or the like) are provided for forming programmable interconnections region to region and/or between the regions. At least some of these interconnection resources are configured in two forms having architecturally similar but significantly different signal transmission speed characteristics. For example, a major or larger portions (200a, 210a, 230a) of the dual-form interconnection resources have what is termed a normal speed, and smaller portions (200b, 210b, 230b) have a significantly faster signal speed.

Abstract translation: 要解决的问题：提供应用于可编程逻辑器件的互连资源，以加速可编程逻辑阵列集成电路器件的工作速度。 解决方案：可编程逻辑集成电路（10）具有多个可编程逻辑区域（20），所述可编程逻辑区域（20）设置在所述多个区域中相交的行和列的阵列中的设备上。 提供互连资源（例如，互连导体等）以形成区域到区域和/或区域之间的可编程互连。 这些互连资源中的至少一些被配置为具有架构上相似但显着不同的信号传输速度特性的两种形式。 例如，双形式互连资源的主要或较大部分（200a，210a，230a）具有所谓的正常速度，较小部分（200b，210b，230b）具有明显更快的信号速度。 版权所有（C）2012，JPO＆INPIT

公开(公告)号：JP2006246534A

公开(公告)日：2006-09-14

申请号：JP2006146010

申请日：2006-05-25

Applicant: Altera Corp ,  アルテラ コーポレイションAltera Corporation

Inventor： NGAI TONY ,  PEDERSEN BRUCE ,  SHUMARAYEV SERGEY ,  SCHLEICHER JAMES ,  HUANG WEI-JEN ,  HUTTON MICHAEL ,  MARURI VICTOR ,  PATEL RAKESH ,  KAZARIAN PETER J ,  LEAVER ANDREW ,  MENDEL DAVID W ,  PARK JIM

IPC: H03K19/177 ,  H01L21/82 ,  H03K19/173

CPC classification number: H03K19/17736 ,  H03K19/1737 ,  H03K19/17728 ,  H03K19/17744

Abstract: PROBLEM TO BE SOLVED: To provide an interconnection resource for applying to a programmable logic device for increasing the operating speed of a programmable logic array integrated circuit device. SOLUTION: A programmable logic integrated circuit device (10) has a plurality of programmable logic regions (20), disposed on the device with a plurality of intersecting the rows and columns of such regions. Interconnection resources for making programmable interconnections to, from and/or between the regions (e.g., interconnecting conductors or the like) are provided on the device. At least some of these interconnection resources are constituted of two forms, that are architecturally similar but that have markedly different signal propagation speed characteristics. For example, a major or larger portion of such dual-form interconnection resources (200a, 210a, 230a) may have what is called a "normal signal speed", while the smaller of the portions (200b, 210b, 230b) has a significantly higher signal speed. COPYRIGHT: (C)2006,JPO&NCIPI

Abstract translation: 要解决的问题：提供用于应用于可编程逻辑器件的互连资源，以提高可编程逻辑阵列集成电路器件的工作速度。 解决方案：可编程逻辑集成电路器件（10）具有多个可编程逻辑区域（20），该多个可编程逻辑区域（20）设置在多个与这些区域的行和列相交的装置上。 用于在区域之间（或连接导体等）进行可编程互连的互连资源设置在该设备上。 这些互连资源中的至少一些由架构上相似但具有明显不同的信号传播速度特性的两种形式构成。 例如，这种双形互连资源（200a，210a，230a）的主要或较大部分可以具有所谓的“正常信号速度”，而较小的部分（200b，210b，230b）具有显着的 信号速度更高。 版权所有（C）2006，JPO＆NCIPI

公开(公告)号：JP2014200106A

公开(公告)日：2014-10-23

申请号：JP2014131068

申请日：2014-06-26

Applicant: アルテラ コーポレイションAltera Corporation ,  Altera Corp ,  アルテラ コーポレイションAltera Corporation

Inventor： NGAI TONY ,  BRUCE PEDERSON ,  SERGEY SCHUMARAVE ,  SCHLEICHER JAMES ,  HUANG WEI-JEN ,  HUTTON MICHAEL ,  MARURI VICTOR ,  PATEL RAKESH ,  KAZARIAN PETER J ,  ANDREW LIEBER ,  MENDEL DAVID W ,  JIM PARK

IPC: H03K19/177 ,  H03K19/173

CPC classification number: H03K19/17736 ,  H03K19/1737 ,  H03K19/17728 ,  H03K19/17744

Abstract: 【課題】プログラマブルロジックデバイスに適用してプログラマブルロジックアレー集積回路デバイスの動作速度を増加するための相互接続リソースの提供。【解決手段】プログラマブルロジック集積回路(10)は、交差する複数の領域の行および列からなる配列をもって、デバイス上に配置された複数のプログラマブルロジック領域(20)を有する。領域から領域へおよび/または領域間におけるプログラム可能な相互接続を形成するための相互接続リソース(例えば、相互接続コンダクタ等)が設けられ、これらのうちの少なくともいくつかは、構造的には類似であるが著しく異なる信号伝送速度特性を有する2つの形式で構成される。例えば、これらの双対形式相互接続リソースのうちの主要なまたは大きな部分(200a,210a,230a)はノーマル速度と呼ばれるものであり、少ないほうの部分(200b,210b,230b)は大幅に高速な信号速度を有する。【選択図】図2

Abstract translation: 要解决的问题：提供应用于可编程逻辑器件的互连资源，以加速可编程逻辑阵列集成电路器件的工作速度。解决方案：可编程逻辑集成电路（10）具有多个可编程逻辑区域（20） 位于所述多个区域中相交的行和列的阵列中的设备。 提供互连资源（例如，互连导体等）以形成区域到区域和/或区域之间的可编程互连。 这些互连资源中的至少一些被配置为具有架构上相似但显着不同的信号传输速度特性的两种形式。 例如，双形式互连资源的主要或较大部分（200a，210a，230a）具有所谓的正常速度，较小部分（200b，210b，230b）具有明显更快的信号速度。

公开(公告)号：JP2012186863A

公开(公告)日：2012-09-27

申请号：JP2012141122

申请日：2012-06-22

Applicant: Altera Corp ,  アルテラ コーポレイションAltera Corporation

Inventor： NGAI TONY ,  BRUCE PEDERSON ,  SERGEY SCHUMARAVE ,  SCHLEICHER JAMES ,  HUANG WEI-JEN ,  HUTTON MICHAEL ,  MARURI VICTOR ,  PATEL RAKESH ,  KAZARIAN PETER J ,  ANDREW LIEBER ,  MENDEL DAVID W ,  JIM PARK

IPC: H03K19/173 ,  H03K19/177

CPC classification number: H03K19/17736 ,  H03K19/1737 ,  H03K19/17728 ,  H03K19/17744

Abstract: PROBLEM TO BE SOLVED: To provide interconnection resources for increasing operation speed of a programmable logic array integrated circuit device, by application on a programmable logic device.SOLUTION: A programmable logic integrated circuit (10) has a plurality of regions (20) of programmable logic disposed on the device in an array consisting of a plurality of intersecting rows and columns of regions. Interconnection resources (e.g., interconnection conductors, etc.) are provided for making programmable interconnections to, from, and/or between the regions. At least some of these interconnection resources are provided in two forms that are architecturally similar but that have significantly different signal propagation speed characteristics. For example, a major or larger portion (200a, 210a, 230a) of such dual-form interconnection resources has speed termed normal speed, while a smaller minor portion (200b, 210b, 230b) has significantly faster signal speed.

Abstract translation: 要解决的问题：通过应用于可编程逻辑器件，提供用于提高可编程逻辑阵列集成电路器件的操作速度的互连资源。 解决方案：可编程逻辑集成电路（10）具有多个可编程逻辑区域（20），该可编程逻辑区域设置在由多个相交的行和列区域组成的阵列中。 互连资源（例如，互连导体等）被提供用于对区域之间，从区域和/或区域之间进行可编程互连。 这些互连资源中的至少一些以架构上相似但具有显着不同的信号传播速度特性的两种形式提供。 例如，这种双形互连资源的主要或较大部分（200a，210a，230a）具有称为正常速度的速度，而较小次要部分（200b，210b，230b）具有明显更快的信号速度。 版权所有（C）2012，JPO＆INPIT