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    Bumping process and structure thereof
    17.
    发明授权
    Bumping process and structure thereof 有权
    冲击过程及其结构

    公开(公告)号：US08658528B2

    公开(公告)日：2014-02-25

    申请号：US13753936

    申请日：2013-01-30

    Applicant: Chipbond Technology Corporation

    Inventor： Chih-Ming Kuo ,  Yie-Chuan Chiu ,  Lung-Hua Ho

    IPC: H01L21/44

    CPC classification number: H01L21/76885 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L2224/034 ,  H01L2224/03912 ,  H01L2224/0401 ,  H01L2224/05027 ,  H01L2224/05184 ,  H01L2224/05572 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/11472 ,  H01L2224/11903 ,  H01L2224/13147 ,  H01L2224/13562 ,  H01L2224/13564 ,  H01L2224/13582 ,  H01L2224/13644 ,  H01L2224/13655 ,  H01L2224/13664 ,  H01L2924/00014 ,  H01L2224/05552

    Abstract: A bumping process includes providing a silicon substrate; forming a titanium-containing metal layer on silicon substrate, the titanium-containing metal layer comprises a plurality of first areas and a plurality of second areas; forming a first photoresist layer on titanium-containing metal layer; patterning the first photoresist layer to form a plurality of first opening slots; forming a plurality of copper bumps within first opening slots, said copper bump comprises a first top surface and a first ring surface; removing the first photoresist layer; forming a second photoresist layer on titanium-containing metal layer; patterning the second photoresist layer to form a plurality of second opening slots; forming a plurality of bump isolation layers at spaces, the first top surfaces and the first ring surfaces; forming a plurality of connective layers on bump isolation layers; removing the second photoresist layer, removing the second areas to form an under bump metallurgy layer.

    Abstract translation: 碰撞过程包括提供硅衬底; 在硅衬底上形成含钛金属层，所述含钛金属层包括多个第一区域和多个第二区域; 在含钛金属层上形成第一光致抗蚀剂层; 图案化第一光致抗蚀剂层以形成多个第一开口槽; 在第一开口槽内形成多个铜凸块，所述铜凸块包括第一上表面和第一环表面; 去除第一光致抗蚀剂层; 在含钛金属层上形成第二光致抗蚀剂层; 图案化所述第二光致抗蚀剂层以形成多个第二开口槽; 在空间，第一顶表面和第一环表面处形成多个凸块隔离层; 在凸块隔离层上形成多个连接层; 去除第二光致抗蚀剂层，去除第二区域以形成凸起下的冶金层。

    CARRIER WITH THREE-DIMENSIONAL CAPACITOR
    19.
    发明申请
    CARRIER WITH THREE-DIMENSIONAL CAPACITOR 有权
    携带三维电容器

    公开(公告)号：US20140008111A1

    公开(公告)日：2014-01-09

    申请号：US13644709

    申请日：2012-10-04

    Applicant: CHIPBOND TECHNOLOGY CORPORATION

    Inventor： Chih-Ming Kuo ,  Lung-Hua Ho ,  You-Ming Hsu

    IPC: H05K1/16 ,  H05K1/02 ,  H05K1/09

    CPC classification number: H01L23/5223 ,  H01G4/01 ,  H01L28/86 ,  H01L2924/0002 ,  H05K1/162 ,  H01L2924/00

    Abstract: A carrier with three-dimensional capacitor includes a substrate and a three-dimensional capacitor, wherein the substrate comprises a trace layer having a first terminal and a second terminal. The three-dimensional capacitor is integrally formed as one piece with the trace layer. The three-dimensional capacitor and the trace layer are made of same material. The three-dimensional capacitor comprises a first capacitance portion and a second capacitance portion, the first capacitance portion comprises a first section, a second section and a first passage, the second capacitance portion is formed at the first passage. The second capacitance portion comprises a third section, a fourth section and a second passage communicated with the first passage. The first capacitance portion is located at the second passage, a first end of the first capacitance portion connects to the first terminal, and a third end of the second capacitance portion connects to the second terminal.

    Abstract translation: 具有三维电容器的载体包括基板和三维电容器，其中所述基板包括具有第一端子和第二端子的迹线层。 三维电容器与轨迹层一体形成。 三维电容器和迹线层由相同的材料制成。 三维电容器包括第一电容部分和第二电容部分，第一电容部分包括第一部分，第二部分和第一通道，第二电容部分形成在第一通道处。 第二电容部分包括与第一通道连通的第三部分，第四部分和第二通道。 第一电容部分位于第二通道处，第一电容部分的第一端连接到第一端子，第二电容部分的第三端连接到第二端子。

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