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公开(公告)号：US20130181346A1
公开(公告)日：2013-07-18
申请号：US13743844
申请日：2013-01-17
Applicant: CHIPBOND TECHNOLOGY CORPORATION
Inventor： Chih-Ming Kuo , Yie-Chuan Chiu , Lung-Hua Ho
IPC: H01L23/498
CPC classification number: H01L23/49811 , H01L24/11 , H01L24/13 , H01L2224/034 , H01L2224/0347 , H01L2224/03912 , H01L2224/0401 , H01L2224/05166 , H01L2224/05572 , H01L2224/05644 , H01L2224/05655 , H01L2224/05664 , H01L2224/11472 , H01L2224/1182 , H01L2224/11906 , H01L2224/13147 , H01L2224/13562 , H01L2224/13564 , H01L2224/13582 , H01L2224/13644 , H01L2224/13655 , H01L2224/13664 , H01L2924/00014 , H01L2924/01074 , H01L2924/01079 , H01L2924/01029 , H01L2924/01028 , H01L2224/05552
Abstract: A bumping process includes providing a silicon substrate, forming a titanium-containing metal layer on the silicon substrate, wherein the titanium-containing metal layer comprises a plurality of first areas and a plurality of second areas, forming a photoresist layer on the titanium-containing metal layer, patterning the photoresist layer to form a plurality of opening slots, forming a plurality of bottom coverage layers at the opening slots, proceeding a heat procedure, forming a plurality of external coverage layers to make each of the external coverage layers connect with each of the bottom coverage layers, wherein said external coverage layer and said bottom coverage layer form a wrap layer and completely surround the copper bump, forming a plurality of connective layers on the external coverage layers, removing the photoresist layer, removing the second areas and enabling each of the first areas to form an under bump metallurgy layer.
Abstract translation: 凸起工艺包括提供硅衬底，在硅衬底上形成含钛金属层，其中含钛金属层包括多个第一区域和多个第二区域，在含钛金属层上形成光致抗蚀剂层 金属层，图案化光致抗蚀剂层以形成多个开口槽，在开口槽处形成多个底部覆盖层，进行热过程，形成多个外部覆盖层，以使每个外部覆盖层与每个 的底部覆盖层，其中所述外部覆盖层和所述底部覆盖层形成包裹层并且完全围绕铜凸块，在外部覆盖层上形成多个连接层，去除光致抗蚀剂层，去除第二区域并使能 每个第一区域形成凸块下的冶金层。
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公开(公告)号：US11651974B2
公开(公告)日：2023-05-16
申请号：US17161818
申请日：2021-01-29
Applicant: CHIPBOND TECHNOLOGY CORPORATION
Inventor： Chih-Ming Kuo , Lung-Hua Ho , You-Ming Hsu , Fei-Jain Wu
CPC classification number: H01L21/561 , H01L21/565 , H01L21/568 , H01L21/78 , H01L23/3107 , H01L23/562
Abstract: A method of fabricating a semiconductor package includes the steps of: disposing semiconductor devices on a carrier; forming an encapsulation on the carrier to cover the semiconductor devices, a recession of the encapsulation includes a strengthening portion and a recessed portion, the strengthening portion protrudes from the recessed portion and surrounds the recessed portion; and removing the strengthening portion of the recession of the encapsulation.
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公开(公告)号：US20230135424A1
公开(公告)日：2023-05-04
申请号：US17896171
申请日：2022-08-26
Applicant: CHIPBOND TECHNOLOGY CORPORATION
Inventor： Shrane-Ning Jenq , Wen-Cheng Hsu , Chen-Yu Wang , Chih-Ming Kuo , Chwan-Tyaw Chen , Lung-Hua Ho
IPC: H01L21/48 , H01L23/498 , H01L21/311 , H01L21/3213 , C23C18/54 , C23C28/02 , C25D7/12
Abstract: A package including a first carrier, a seed layer, wires, a die and a molding material is provided. The first carrier is removed to expose the seed layer after disposing a second carrier on the molding material, then the seed layer is removed to expose the wires, and a gold layer is deposited on each of the wires by immersion gold plating, finally a semiconductor device is obtained. The gold layer is provided to protect the wires from oxidation and improve solder joint reliability.
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公开(公告)号：US09159660B2
公开(公告)日：2015-10-13
申请号：US14042979
申请日：2013-10-01
Applicant: CHIPBOND TECHNOLOGY CORPORATION
Inventor： Chin-Tang Hsieh , Chih-Ming Kuo , Chia-Jung Tu , Shih-Chieh Chang , Chih-Hsien Ni , Lung-Hua Ho , Chaun-Yu Wu , Kung-An Lin
IPC: H01L23/498 , H01L23/31 , H01L21/56 , H01L23/00 , H01L25/065 , H01L21/48
CPC classification number: H01L23/49811 , H01L21/4846 , H01L21/563 , H01L23/3128 , H01L23/49816 , H01L24/11 , H01L24/13 , H01L24/16 , H01L24/81 , H01L25/0657 , H01L2224/1147 , H01L2224/11472 , H01L2224/11831 , H01L2224/11903 , H01L2224/11906 , H01L2224/13011 , H01L2224/13017 , H01L2224/13019 , H01L2224/13082 , H01L2224/13083 , H01L2224/13084 , H01L2224/131 , H01L2224/13144 , H01L2224/13147 , H01L2224/13155 , H01L2224/16058 , H01L2224/8114 , H01L2224/81193 , H01L2224/81345 , H01L2225/06513 , H01L2225/06565 , H01L2924/00014 , H01L2924/014
Abstract: A semiconductor package structure includes a first substrate, a second substrate and an encapsulant. The first substrate comprises a plurality of first bumps and a plurality of first solder layers. Each of the first solder layers is formed on each of the first bumps and comprises a cone-shaped slot having an inner surface. The second substrate comprises a plurality of second bumps and a plurality of second solder layers. Each of the second solder layers is formed on each of the second bumps and comprises an outer surface. Each of the second solder layers is a cone-shaped body. The second solder layer couples to the first solder layer and is accommodated within the first solder layer. The inner surface of the cone-shaped slot contacts with the outer surface of the second solder layer. The encapsulant is formed between the first substrate and the second substrate.
Abstract translation: 半导体封装结构包括第一衬底，第二衬底和密封剂。 第一基板包括多个第一凸块和多个第一焊料层。 每个第一焊料层形成在每个第一凸块上，并且包括具有内表面的锥形槽。 第二基板包括多个第二凸块和多个第二焊料层。 每个第二焊料层形成在每个第二凸块上并且包括外表面。 每个第二焊料层是锥形体。 第二焊料层耦合到第一焊料层并且容纳在第一焊料层内。 锥形槽的内表面与第二焊料层的外表面接触。 密封剂形成在第一基板和第二基板之间。
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公开(公告)号：US20140141606A1
公开(公告)日：2014-05-22
申请号：US14164628
申请日：2014-01-27
Applicant: Chipbond Technology Corporation
Inventor： Chih-Ming Kuo , Lung-Hua Ho , Shih-Chieh Chang , Chia-Yeh Huang , Chin-Tang Hsieh
IPC: H01L21/768
CPC classification number: H01L21/76885 , H01L21/4853 , H01L23/48 , H01L23/49811 , H01L24/11 , H01L24/13 , H01L2224/0401 , H01L2224/05568 , H01L2224/05644 , H01L2224/05647 , H01L2224/1147 , H01L2224/11849 , H01L2224/11903 , H01L2224/13006 , H01L2224/13016 , H01L2224/13023 , H01L2224/13076 , H01L2224/13082 , H01L2224/13083 , H01L2224/13144 , H01L2224/13147 , H01L2224/13155 , H01L2924/00014 , H01L2924/00012 , H01L2224/05552
Abstract: A semiconductor manufacturing method includes providing a carrier; forming a first photoresist layer; forming plural core portions; removing the first photoresist layer; forming a second photoresist layer; forming a plurality of connection portions, each of the plurality of connection portions includes a first connection layer and a second connection layer and connects to each of the core portions to form a hybrid bump, wherein each of the first connection layers comprises a base portion, a projecting portion and an accommodating space, each base portion comprises an upper surface, each projecting portion is protruded to the upper surface and located on top of each core portion, each accommodating space is located outside each projecting portion, the second connection layers cover the projecting portions and the upper surfaces, and the accommodating spaces are filled by the second connection layers; removing the second photoresist layer to reveal the hybrid bumps.
Abstract translation: 半导体制造方法包括提供载体; 形成第一光致抗蚀剂层; 形成多个芯部; 去除第一光致抗蚀剂层; 形成第二光致抗蚀剂层; 形成多个连接部分，所述多个连接部分中的每一个包括第一连接层和第二连接层，并且连接到每个所述芯部分以形成混合凸块，其中每个所述第一连接层包括基部， 突出部分和容纳空间，每个基部包括上表面，每个突出部分突出到上表面并且位于每个芯部的顶部，每个容纳空间位于每个突出部分的外侧，第二连接层覆盖 突出部分和上表面，并且容纳空间被第二连接层填充; 去除第二光致抗蚀剂层以露出混合凸块。
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Patent Agency Ranking
公开(公告)号：US20140117540A1
公开(公告)日：2014-05-01
申请号：US14148038
申请日：2014-01-06
Applicant: CHIPBOND TECHNOLOGY CORPORATION
Inventor： Chih-Ming Kuo , Lung-Hua Ho , Kung-An Lin , Sheng-Hui Chen
IPC: H01L23/00
CPC classification number: H01L24/14 , H01L21/4853 , H01L23/49811 , H01L24/11 , H01L24/13 , H01L2224/0401 , H01L2224/05166 , H01L2224/05568 , H01L2224/05644 , H01L2224/05647 , H01L2224/1147 , H01L2224/11849 , H01L2224/11903 , H01L2224/13006 , H01L2224/13017 , H01L2224/13023 , H01L2224/13076 , H01L2224/13082 , H01L2224/13083 , H01L2224/131 , H01L2224/13144 , H01L2224/13147 , H01L2224/13155 , H01L2924/00014 , H01L2924/014 , H01L2224/05552
Abstract: A semiconductor manufacturing method includes providing a substrate having a metallic layer that includes a first metal layer and a second metal layer, the first metal layer comprises plural base areas and plural first outer lateral areas, the second metal layer comprises plural second base areas and plural second outer lateral areas; forming a first photoresist layer; forming plural bearing portions; removing the first photoresist layer; forming a second photoresist layer; forming plural connection portions, each connection portion comprises a first connection layer and a second connection layer; removing the second photoresist layer to reveal the connection portions and the bearing portions; removing the first outer lateral areas; reflowing the second connection layers to form plural composite bumps; removing the second outer lateral areas to make the first base areas and the second base areas form plural under bump metallurgy layers.
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公开(公告)号：US08658528B2
公开(公告)日：2014-02-25
申请号：US13753936
申请日：2013-01-30
Applicant: Chipbond Technology Corporation
Inventor： Chih-Ming Kuo , Yie-Chuan Chiu , Lung-Hua Ho
IPC: H01L21/44
CPC classification number: H01L21/76885 , H01L24/03 , H01L24/05 , H01L24/11 , H01L24/13 , H01L2224/034 , H01L2224/03912 , H01L2224/0401 , H01L2224/05027 , H01L2224/05184 , H01L2224/05572 , H01L2224/05644 , H01L2224/05647 , H01L2224/11472 , H01L2224/11903 , H01L2224/13147 , H01L2224/13562 , H01L2224/13564 , H01L2224/13582 , H01L2224/13644 , H01L2224/13655 , H01L2224/13664 , H01L2924/00014 , H01L2224/05552
Abstract: A bumping process includes providing a silicon substrate; forming a titanium-containing metal layer on silicon substrate, the titanium-containing metal layer comprises a plurality of first areas and a plurality of second areas; forming a first photoresist layer on titanium-containing metal layer; patterning the first photoresist layer to form a plurality of first opening slots; forming a plurality of copper bumps within first opening slots, said copper bump comprises a first top surface and a first ring surface; removing the first photoresist layer; forming a second photoresist layer on titanium-containing metal layer; patterning the second photoresist layer to form a plurality of second opening slots; forming a plurality of bump isolation layers at spaces, the first top surfaces and the first ring surfaces; forming a plurality of connective layers on bump isolation layers; removing the second photoresist layer, removing the second areas to form an under bump metallurgy layer.
Abstract translation: 碰撞过程包括提供硅衬底; 在硅衬底上形成含钛金属层，所述含钛金属层包括多个第一区域和多个第二区域; 在含钛金属层上形成第一光致抗蚀剂层; 图案化第一光致抗蚀剂层以形成多个第一开口槽; 在第一开口槽内形成多个铜凸块，所述铜凸块包括第一上表面和第一环表面; 去除第一光致抗蚀剂层; 在含钛金属层上形成第二光致抗蚀剂层; 图案化所述第二光致抗蚀剂层以形成多个第二开口槽; 在空间，第一顶表面和第一环表面处形成多个凸块隔离层; 在凸块隔离层上形成多个连接层; 去除第二光致抗蚀剂层，去除第二区域以形成凸起下的冶金层。
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公开(公告)号：US20140027905A1
公开(公告)日：2014-01-30
申请号：US14042979
申请日：2013-10-01
Applicant: CHIPBOND TECHNOLOGY CORPORATION
Inventor： Chin-Tang Hsieh , Chih-Ming Kuo , Chia-Jung Tu , Shih-Chieh Chang , Chih-Hsien Ni , Lung-Hua Ho , Chaun-Yu Wu , Kung-An Lin
IPC: H01L23/498
CPC classification number: H01L23/49811 , H01L21/4846 , H01L21/563 , H01L23/3128 , H01L23/49816 , H01L24/11 , H01L24/13 , H01L24/16 , H01L24/81 , H01L25/0657 , H01L2224/1147 , H01L2224/11472 , H01L2224/11831 , H01L2224/11903 , H01L2224/11906 , H01L2224/13011 , H01L2224/13017 , H01L2224/13019 , H01L2224/13082 , H01L2224/13083 , H01L2224/13084 , H01L2224/131 , H01L2224/13144 , H01L2224/13147 , H01L2224/13155 , H01L2224/16058 , H01L2224/8114 , H01L2224/81193 , H01L2224/81345 , H01L2225/06513 , H01L2225/06565 , H01L2924/00014 , H01L2924/014
Abstract: A semiconductor package structure includes a first substrate, a second substrate and an encapsulant. The first substrate comprises a plurality of first bumps and a plurality of first solder layers. Each of the first solder layers is formed on each of the first bumps and comprises a cone-shaped slot having an inner surface. The second substrate comprises a plurality of second bumps and a plurality of second solder layers. Each of the second solder layers is formed on each of the second bumps and comprises an outer surface. Each of the second solder layers is a cone-shaped body. The second solder layer couples to the first solder layer and is accommodated within the first solder layer. The inner surface of the cone-shaped slot contacts with the outer surface of the second solder layer. The encapsulant is formed between the first substrate and the second substrate.
Abstract translation: 半导体封装结构包括第一衬底，第二衬底和密封剂。 第一基板包括多个第一凸块和多个第一焊料层。 每个第一焊料层形成在每个第一凸块上，并且包括具有内表面的锥形槽。 第二基板包括多个第二凸块和多个第二焊料层。 每个第二焊料层形成在每个第二凸块上并且包括外表面。 每个第二焊料层是锥形体。 第二焊料层耦合到第一焊料层并且容纳在第一焊料层内。 锥形槽的内表面与第二焊料层的外表面接触。 密封剂形成在第一基板和第二基板之间。
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公开(公告)号：US20140008111A1
公开(公告)日：2014-01-09
申请号：US13644709
申请日：2012-10-04
Applicant: CHIPBOND TECHNOLOGY CORPORATION
Inventor： Chih-Ming Kuo , Lung-Hua Ho , You-Ming Hsu
CPC classification number: H01L23/5223 , H01G4/01 , H01L28/86 , H01L2924/0002 , H05K1/162 , H01L2924/00
Abstract: A carrier with three-dimensional capacitor includes a substrate and a three-dimensional capacitor, wherein the substrate comprises a trace layer having a first terminal and a second terminal. The three-dimensional capacitor is integrally formed as one piece with the trace layer. The three-dimensional capacitor and the trace layer are made of same material. The three-dimensional capacitor comprises a first capacitance portion and a second capacitance portion, the first capacitance portion comprises a first section, a second section and a first passage, the second capacitance portion is formed at the first passage. The second capacitance portion comprises a third section, a fourth section and a second passage communicated with the first passage. The first capacitance portion is located at the second passage, a first end of the first capacitance portion connects to the first terminal, and a third end of the second capacitance portion connects to the second terminal.
Abstract translation: 具有三维电容器的载体包括基板和三维电容器，其中所述基板包括具有第一端子和第二端子的迹线层。 三维电容器与轨迹层一体形成。 三维电容器和迹线层由相同的材料制成。 三维电容器包括第一电容部分和第二电容部分，第一电容部分包括第一部分，第二部分和第一通道，第二电容部分形成在第一通道处。 第二电容部分包括与第一通道连通的第三部分，第四部分和第二通道。 第一电容部分位于第二通道处，第一电容部分的第一端连接到第一端子，第二电容部分的第三端连接到第二端子。
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公开(公告)号：US12224183B2
公开(公告)日：2025-02-11
申请号：US17896171
申请日：2022-08-26
Applicant: CHIPBOND TECHNOLOGY CORPORATION
Inventor： Shrane-Ning Jenq , Wen-Cheng Hsu , Chen-Yu Wang , Chih-Ming Kuo , Chwan-Tyaw Chen , Lung-Hua Ho
IPC: H01L21/48 , C23C18/54 , C23C28/02 , C25D7/12 , H01L21/311 , H01L21/3213 , H01L23/498 , H01L23/00
Abstract: A package including a first carrier, a seed layer, wires, a die and a molding material is provided. The first carrier is removed to expose the seed layer after disposing a second carrier on the molding material, then the seed layer is removed to expose the wires, and a gold layer is deposited on each of the wires by immersion gold plating, finally a semiconductor device is obtained. The gold layer is provided to protect the wires from oxidation and improve solder joint reliability.
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