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    11.
    发明专利
    未知

    公开(公告)号：DE69132539D1

    公开(公告)日：2001-03-29

    申请号：DE69132539

    申请日：1991-08-30

    Applicant: IBM

    Inventor： ALDEREGUIA ALFREDO ,  CROMER DARYL CARVIS ,  STUTES ROGER MAX

    IPC: G06F12/06 ,  G11C8/12

    Abstract: A data processing system includes a processor for accessing a memory in either a direct mode or an indirect mode. The memory includes at least two memory banks and two decoders for decoding bank addresses. The decoders produce bank select signals. In direct mode, the decoder outputs are generated according to which bank is addressed. In interleave mode, the two decoder outputs are ANDed to select both banks covering the address range of the selected banks.

    13.
    发明专利
    未知

    公开(公告)号：DE69124905D1

    公开(公告)日：1997-04-10

    申请号：DE69124905

    申请日：1991-08-30

    Applicant: IBM

    Inventor： ALDEREGUIA ALFREDO ,  CROMER DARYL CARVIS ,  BLAND PATRICK MAURICE ,  STUTES ROGER MAX

    IPC: G11C11/401 ,  G06F12/00 ,  G06F12/02 ,  G06F12/06 ,  G06F13/42 ,  G11C11/407

    Abstract: A data processing system includes a memory controller for accessing a dynamic memory having a plurality of SIMMs that differ in size and speed of operation. The memory controller is operable in response to a request to access a given SIMM to read a SIMM definition register and dynamically produce memory access signals in accordance with the timing requirements of the particular SIMM being accessed. Such signals are set each time a SIMM is accessed. The signals provide different clock periods of RAS precharge time, RAS to CAS time, and CAS pulse width.

    16.
    发明专利
    未知

    公开(公告)号：FI914608A0

    公开(公告)日：1991-10-01

    申请号：FI914608

    申请日：1991-10-01

    Applicant: IBM

    Inventor： ALDEREGUIA ALFREDO ,  BLAND PATRICK MAURICE ,  CROMER DARYL CARVIS ,  STUTES ROGER MAX

    IPC: G11C11/401 ,  G06F12/00 ,  G06F12/02 ,  G06F12/06 ,  G06F13/42 ,  G11C11/407 ,  G11C

    Abstract: A data processing system includes a memory controller for accessing a dynamic memory having a plurality of SIMMs that differ in size and speed of operation. The memory controller is operable in response to a request to access a given SIMM to read a SIMM definition register and dynamically produce memory access signals in accordance with the timing requirements of the particular SIMM being accessed. Such signals are set each time a SIMM is accessed. The signals provide different clock periods of RAS precharge time, RAS to CAS time, and CAS pulse width.

    MEMORY CONTROLLER FOR DIRECT OR INTERLEAVE MEMORY ACCESSING
    19.
    发明专利
    MEMORY CONTROLLER FOR DIRECT OR INTERLEAVE MEMORY ACCESSING 未知

    公开(公告)号：CA2050950C

    公开(公告)日：1996-01-02

    申请号：CA2050950

    申请日：1991-09-11

    Applicant: IBM

    Inventor： ALDEREGUIA ALFREDO ,  CROMER DARYL C ,  STUTES RODGER M

    IPC: G06F12/06 ,  G11C8/12

    Abstract: A data processing system includes a processor for accessing a memory in either a direct mode or an indirect mode. The memory includes at least two memory banks and two decoders for decoding bank addresses. The decoders produce bank select signals. In direct mode, the decoder outputs are generated according to which bank is addressed. In interleave mode, the two decoder outputs are ANDed to select both banks covering the address range of the selected banks.

    Bus interface logic for computer system having dual bus architecture
    20.
    发明专利
    Bus interface logic for computer system having dual bus architecture 未知

    公开(公告)号：AU652707B2

    公开(公告)日：1994-09-01

    申请号：AU2979592

    申请日：1992-12-02

    Applicant: IBM

    Inventor： ALDEREGUIA ALFREDO ,  AMINI NADER ,  HORNE RICHARD LOUIS ,  LOHMAN TERENCE JOSEPH ,  TRAN CANG NGOC

    IPC: G06F13/36 ,  G06F13/16 ,  G06F13/42 ,  G06F13/00

    Abstract: A computer system is provided, comprising system memory and a memory controller for controlling access to system memory, a central processing unit electrically connected with the memory controller, and a bus interface unit electrically connected to the memory controller by a system bus and electrically connected to an input/output device by an input/output bus. The bus interface unit includes translation logic for temporarily storing, in response to a predetermined set of operating conditions, data transferred between the system bus and the input/output bus through the bus interface unit. The predetermined set of operating conditions occur when (i) the memory controller on behalf of the central processing unit writes data to the input/output device, or (ii) the memory controller on behalf of the central processing unit initiates a read or write cycle destined for the input/output device acting as a slave on the input/output bus, and the data bus width of the memory controller is greater than a corresponding data bus width of the input/output device.

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