公开(公告)号：EP1356507A4

公开(公告)日：2008-05-21

申请号：EP01996224

申请日：2001-12-30

Applicant: IBM

Inventor： GIEWONT KENNETH J ,  BRODSKY STEPHEN BRUCE ,  CABRAL CYRIL JR ,  DOMENICUCCI ANTHONY G ,  RANSOM CRAIG MITCHELL ,  WANG YUN-YU ,  WILDMAN HORATIO S ,  WONG KWONG HON

IPC: C23C14/06 ,  C23C14/34 ,  H01L21/28 ,  H01L21/285 ,  H01L29/423 ,  H01L29/49 ,  H01L29/78 ,  H01L21/44

CPC classification number: C23C14/0094 ,  C23C14/0641 ,  H01L21/28052 ,  H01L21/28518 ,  H01L21/2855

Abstract: A method is provided for forming a capping layer for a semiconductor structure including a silicide-forming metal (2) overlying silicon (1). According to the invention, a layer of nitride (51) is formed overlying the semiconductor structure and in contact with the silicide-forming metal (2). This layer is formed by sputtering form a target in an ambient characterized by a nitrogen flow less than about 45 sccm. The layer is therefore deficient in nitrogen, so that formation of an oxynitride at a native oxide layer (11) on the silicon is avoided and diffusion between the silicon (1) and the metal (2) is not inhibited.

公开(公告)号：WO0231867A3

公开(公告)日：2002-10-17

申请号：PCT/GB0104430

申请日：2001-10-05

Applicant: IBM ,  IBM UK

Inventor： CABRAL CYRIL JR ,  CLEVENGER LAWRENCE ,  HSU LOUIS LU-CHEN ,  WONG KWONG HON

IPC: H01L21/02 ,  H01L27/06

CPC classification number: H01L28/20 ,  H01L27/0688

Abstract: Electronic structure that has in-situ formed resistors consists of a first plurality of conductive elements formed in an insulating material layer, a plurality of electrically resistive vias formed on top and in electrical communication with at least one of the first plurality of conductive elements, and a second plurality of conductive elements formed on top of and in electrical communication with at least one of the plurality of electrically resistive vias. The structure may further be formed in a multi-level configuration such that multi-level resistors may be connected in-series to provide larger resistance values. The structure may be combined with a capacitor network to form RC circuits.

Abstract translation: 具有原位形成的电阻器的电子结构由形成在绝缘材料层中的第一多个导电元件，形成在顶部上并与第一多个导电元件中的至少一个电连通的多个电阻通孔，以及 形成在所述多个电阻通孔中的至少一个上方并与之电气连通的第二多个导电元件。 该结构还可以形成为多电平配置，使得多电平电阻器可以串联连接以提供更大的电阻值。 该结构可以与电容器网络组合以形成RC电路。

公开(公告)号：WO2007011438A2

公开(公告)日：2007-01-25

申请号：PCT/US2006013173

申请日：2006-04-07

Applicant: IBM ,  CABRAL CYRIL JR ,  GORDON MICHAEL S ,  RODBELL KENNETH P

Inventor： CABRAL CYRIL JR ,  GORDON MICHAEL S ,  RODBELL KENNETH P

IPC: H01L23/52 ,  H01L23/48 ,  H01L29/40

CPC classification number: H01L23/556 ,  H01L21/76801 ,  H01L21/76834 ,  H01L21/76838 ,  H01L23/5329 ,  H01L23/53295 ,  H01L23/585 ,  H01L24/03 ,  H01L24/05 ,  H01L24/12 ,  H01L24/16 ,  H01L24/45 ,  H01L24/48 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05006 ,  H01L2224/05554 ,  H01L2224/05572 ,  H01L2224/05599 ,  H01L2224/13007 ,  H01L2224/13022 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/16 ,  H01L2224/451 ,  H01L2224/48227 ,  H01L2224/48465 ,  H01L2224/85399 ,  H01L2924/00014 ,  H01L2924/0002 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01007 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/0102 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01027 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01044 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01055 ,  H01L2924/01057 ,  H01L2924/01063 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/01084 ,  H01L2924/01092 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/05042 ,  H01L2924/10253 ,  H01L2924/1305 ,  H01L2924/1306 ,  H01L2924/14 ,  H01L2924/15174 ,  H01L2924/15312 ,  H01L2924/15787 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/30107 ,  H01L2924/3025 ,  H01L2224/45099 ,  H01L2924/00 ,  H01L2224/05552

Abstract: A structure and a method for reduction of soft error rates in integrated circuits. The structure including: a semiconductor substrate; and a stack of one or more wiring levels stacked from a lowermost wiring level to an uppermost wiring level, the lowermost wiring level nearer the semiconductor substrate than the uppermost wiring level; and an alpha particle blocking layer on a top surface of the uppermost wiring level of the one or more wiring levels, the blocking layer comprising metal wires and a dielectric material, the blocking layer having a combination of a thickness of the blocking layer and a volume percent of metal wires in the blocking layer sufficient to stop a predetermined percentage of alpha particles of a selected energy or less striking the blocking layer from penetrating into the stack of one or more wiring levels or the substrate.

Abstract translation: 降低集成电路中软错误率的结构和方法。 该结构包括：半导体衬底; 以及从最下层布线层到最上布线层叠的一层以上的布线层叠层，比最上布线层更靠近半导体基板的最下布线层; 以及在所述一个或多个布线层的最上布线层的顶表面上的α粒子阻挡层，所述阻挡层包括金属线和介电材料，所述阻挡层具有阻挡层的厚度和体积 阻挡层中的金属线的百分比足以阻止预定百分比的选定能量的α粒子或更少的击穿阻挡层的金属线穿透到一个或多个布线层或衬底的堆叠中。

公开(公告)号：WO2006060574A3

公开(公告)日：2006-07-20

申请号：PCT/US2005043473

申请日：2005-12-01

Applicant: IBM ,  FANG SUNFEI ,  CABRAL CYRIL JR ,  DZIOBKOWSKI CHESTER T ,  LAVOIE CHRISTIAN ,  WANN CLEMENT H

Inventor： FANG SUNFEI ,  CABRAL CYRIL JR ,  DZIOBKOWSKI CHESTER T ,  LAVOIE CHRISTIAN ,  WANN CLEMENT H

IPC: H01L21/8238

CPC classification number: H01L21/823835

Abstract: A method of forming a dual self-aligned fully silicided gate in a CMOS device requiring only one lithography level, wherein the method comprises forming a first type semiconductor device (270) having a first well region (253) in a semiconductor substrate (252), first source/drain silicide areas (266) in the first well region (253), and a first type gate (263) isolated from the first source/drain silicide areas (266); forming a second type semiconductor device (280) having a second well region (254) in the semiconductor substrate (252), second source/drain silicide areas (256) in the second well region (254), and a second type gate (258) isolated from the second source/drain silicide areas (256); selectively forming a first metal layer (218) over the second type semiconductor device (280); performing a first fully silicided (FUSI) gate formation on only the second type gate (258); depositing a second metal layer (275) over the first and second type semiconductor devices (270,280); and performing a second FUSI gate formation on only the first type gate (263).

Abstract translation: 一种在仅需要一个光刻级别的CMOS器件中形成双自对准全硅化栅极的方法，其中该方法包括在半导体衬底（252）中形成具有第一阱区（253）的第一类型半导体器件（270） ，第一阱区（253）中的第一源极/漏极硅化物区域（266）以及与第一源极/漏极硅化物区域（266）隔离的第一类型栅极（263）; 形成具有半导体衬底（252）中的第二阱区（254），第二阱区（254）中的第二源极/漏极硅化物区（256）和第二类型栅极（258）的第二类型半导体器件 ）与第二源极/漏极硅化物区域（256）隔离; 在所述第二类型半导体器件（280）上方选择性地形成第一金属层（218）; 仅在所述第二类型栅极（258）上执行第一全硅化物（FUSI）栅极形成; 在第一和第二类型半导体器件（270,280）上沉积第二金属层（275）; 以及仅在第一类型栅极（263）上执行第二FUSI栅极形成。

公开(公告)号：WO2005083780A2

公开(公告)日：2005-09-09

申请号：PCT/US2005005565

申请日：2005-02-22

Applicant: IBM ,  AMOS RICKY S ,  BOYD DIANE C ,  CABRAL CYRIL JR ,  KAPLAN RICHARD D ,  KEDZIERSKI JAKUB T ,  KU VICTOR ,  LEE WOO-HYEONG ,  LI YING ,  MOCUTA ANDA C ,  NARAYANAN VIJAY ,  STEEGEN AN L ,  SURENDRA MAHESWAREN

Inventor： AMOS RICKY S ,  BOYD DIANE C ,  CABRAL CYRIL JR ,  KAPLAN RICHARD D ,  KEDZIERSKI JAKUB T ,  KU VICTOR ,  LEE WOO-HYEONG ,  LI YING ,  MOCUTA ANDA C ,  NARAYANAN VIJAY ,  STEEGEN AN L ,  SURENDRA MAHESWAREN

IPC: H01L21/28 ,  H01L21/336 ,  H01L21/339 ,  H01L21/60 ,  H01L21/8238 ,  H01L27/092

CPC classification number: H01L21/76897 ,  H01L21/28052 ,  H01L21/28097 ,  H01L21/823835 ,  H01L29/66545 ,  H01L29/6656

Abstract: The present invention provides a complementary metal oxide semiconductor integration process whereby a plurality of silicided metal gates are fabricated atop a gate dielectric. Each silicided metal gate that is formed using the integration scheme of the present invention has the same silicide metal phase and substantially the same height, regardless of the dimension of the silicide metal gate. The present invention also provides various methods of forming a CMOS structure having silicided contacts in which the polySi gate heights are substantially the same across the entire surface of a semiconductor structure.

Abstract translation: 本发明提供了互补金属氧化物半导体集成工艺，由此在栅极电介质顶上制造多个硅化金属栅极。 不管硅化物金属栅极的尺寸如何，使用本发明的集成方案形成的每个硅化金属栅极具有相同的硅化物金属相和基本相同的高度。 本发明还提供了形成具有硅化触点的CMOS结构的各种方法，其中多晶硅栅极高度在半导体结构的整个表面上基本相同。

公开(公告)号：WO2005122286A3

公开(公告)日：2009-04-16

申请号：PCT/US2005010825

申请日：2005-03-30

Applicant: IBM ,  BOJARCZUK NESTOR A JR ,  CABRAL CYRIL JR ,  CARTIER EDUARD A ,  COPEL MATTHEW W ,  FRANK MARTIN M ,  GOUSEV EVGENI P ,  GUHA SUPRATIK ,  JAMMY RAJARAO ,  NARAYANAN VIJAY ,  PARUCHURI VAMSI K

Inventor： BOJARCZUK NESTOR A JR ,  CABRAL CYRIL JR ,  CARTIER EDUARD A ,  COPEL MATTHEW W ,  FRANK MARTIN M ,  GOUSEV EVGENI P ,  GUHA SUPRATIK ,  JAMMY RAJARAO ,  NARAYANAN VIJAY ,  PARUCHURI VAMSI K

IPC: H01L29/792 ,  H01L21/28 ,  H01L21/8238 ,  H01L29/49 ,  H01L29/51 ,  H01L31/113 ,  H01L31/119

CPC classification number: H01L29/513 ,  H01L21/28079 ,  H01L21/28088 ,  H01L21/823857 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/517

Abstract: A method of forming a CMOS structure, and the device produced therefrom, having improved threshold voltage and flatband voltage stability. The inventive method includes the steps of providing a semiconductor substrate having an nFET region and a pFET region; forming a dielectric stack atop the semiconductor substrate comprisisng an insulating interlayer atop a high k dielectric; removing the insulating interlayer from the nFET region without removing the insulating interlayer from the pFET region; and providing at least one gate stack in the pFET region and at least one gate stack in the nFET region. The insulating interlayer can be A1N or A1OxNY. The high k dielectric can be HfO2, hafnium silicate or hafnium silicon oxynitride. The insulating interlayer can be removed from the nFET region by a wet etch including a HC1/H2O2 peroxide solution.

Abstract translation: 一种形成CMOS结构的方法及其制造的器件，具有改进的阈值电压和平带电压稳定性。 本发明的方法包括提供具有nFET区和pFET区的半导体衬底的步骤; 在半导体衬底顶部形成介电堆叠，其中包括在高k电介质顶部的绝缘夹层; 从nFET区域去除绝缘中间层而不从pFET区域去除绝缘中间层; 以及在pFET区域中提供至少一个栅极堆叠以及在nFET区域中提供至少一个栅极叠层。 绝缘中间层可以是AlN或AlOxNY。 高k电介质可以是HfO 2，硅酸铪或铪硅氮氧化物。 可以通过包括HC1 / H2O2过氧化物溶液的湿蚀刻从nFET区域去除绝缘中间层。

公开(公告)号：WO2004027824A2

公开(公告)日：2004-04-01

申请号：PCT/US0329085

申请日：2003-09-16

Applicant: INFINEON TECHNOLOGIES AG ,  IBM ,  SCHUTZ RONALD J ,  ROBL WERNER ,  MALIK RAJEEV ,  CLEVENGER LARRY ,  GLUSCHENKOV OLEG ,  CABRAL CYRIL JR ,  IGGULDEN ROY C ,  WANG YUN-YU ,  WONG KWONG HON ,  MCSTAY IRENE

Inventor： SCHUTZ RONALD J ,  ROBL WERNER ,  MALIK RAJEEV ,  CLEVENGER LARRY ,  GLUSCHENKOV OLEG ,  CABRAL CYRIL JR ,  IGGULDEN ROY C ,  WANG YUN-YU ,  WONG KWONG HON ,  MCSTAY IRENE

IPC: H01L20060101 ,  H01L21/28 ,  H01L21/3205 ,  H01L21/336 ,  H01L21/4763 ,  H01L21/768 ,  H01L23/522 ,  H01L29/40 ,  H01L29/51 ,  H01L29/78 ,  H01L

CPC classification number: H01L21/7685 ,  H01L21/28052 ,  H01L21/28061 ,  H01L21/76838 ,  H01L21/76855 ,  H01L21/823828 ,  H01L21/823842 ,  H01L29/4941 ,  H01L29/51 ,  H01L29/517 ,  H01L29/518 ,  H01L29/78 ,  H01L2221/1078

Abstract: A conductive structure in an integrated circuit (12), and a method of forming the structure, is provided that includes a polysilicon layer (30), a thin layer containing titanium over the polysilicon, a tungsten nitride layer (34) over the titanium-containing layer and a tungsten layer over the tungsten nitride layer. The structure also includes a silicon nitride interfacial region (38) between the polysilicon layer and the titanium-containing layer. The structure withstands high-temperature processing without substantial formation of metal silicides in the polysilicon layer (30) and the tungsten layer (32), and provides low interface resistance between the tungsten layer and the polysilicon layer.

Abstract translation: 提供了集成电路（12）中的导电结构以及形成该结构的方法，该导电结构包括多晶硅层（30），在多晶硅上包含钛的薄层，在钛 - 氮化镓层上的氮化钨层（34） 在氮化钨层上形成含钨层和钨层。 该结构还包括在多晶硅层和含钛层之间的氮化硅界面区域（38）。 该结构耐受高温处理而在多晶硅层（30）和钨层（32）中基本上不形成金属硅化物，并且在钨层和多晶硅层之间提供低的界面电阻。

公开(公告)号：WO2007016514A3

公开(公告)日：2007-04-05

申请号：PCT/US2006029800

申请日：2006-08-01

Applicant: IBM ,  NAYFEH HASAN M ,  KUMAR MAHENDER ,  FANG SUNFEI ,  KEDZIERSKI JAKUB T ,  CABRAL CYRIL JR

Inventor： NAYFEH HASAN M ,  KUMAR MAHENDER ,  FANG SUNFEI ,  KEDZIERSKI JAKUB T ,  CABRAL CYRIL JR

IPC: H01L21/8238 ,  H01L21/336 ,  H01L21/4763 ,  H01L21/8234 ,  H01L29/00

CPC classification number: H01L21/823835 ,  H01L21/823842 ,  H01L29/66545 ,  H01L29/6659 ,  H01L29/7833

Abstract: A MOSFET structure and method of forming is described. The method includes forming a metal-containing layer (56) that is thick enough to fully convert the semiconductor layer (22) to a semiconductor metal alloy in a first MOSFET type region (40) but only thick enough to partially convert the semiconductor layer (20) to a semiconductor metal alloy in a second MOSFET type region (30). In one embodiment, the gate stack in a first MOSFET region (40) is recessed prior to forming the metal-containing layer (56) so that the height of the first MOSFET semiconductor stack is less than the height of the second MOSFET semiconductor stack. In another embodiment, the metal-containing layer (56) is thinned over a first type MOSFET region (40) relative to a second type MOSFET region (30) prior to the conversion process.

Abstract translation: 描述了MOSFET结构和形成方法。 该方法包括形成足够厚的含金属层（56），以将半导体层（22）完全转换为第一MOSFET型区域（40）中的半导体金属合金，但仅足够厚以部分地转换半导体层（ 20）连接到第二MOSFET型区域（30）中的半导体金属合金。 在一个实施例中，在形成含金属层（56）之前，第一MOSFET区域（40）中的栅极堆叠是凹进的，使得第一MOSFET半导体堆叠的高度小于第二MOSFET半导体堆叠的高度。 在另一个实施例中，在转换过程之前，相对于第二类型MOSFET区域（30），含金属层（56）在第一类型MOSFET区域（40）上变薄。

公开(公告)号：WO2006060575A2

公开(公告)日：2006-06-08

申请号：PCT/US2005043474

申请日：2005-12-01

Applicant: IBM ,  CABRAL CYRIL JR ,  DZIOBKOWSKI CHESTER T ,  ELLIS-MONAGHAN JOHN J ,  FANG SUNFEI ,  LAVOIE CHRISTIAN ,  LUO ZHIJIONG ,  NAKOS JAMES S ,  STEEGEN AN L ,  WANN CLEMENT H

Inventor： CABRAL CYRIL JR ,  DZIOBKOWSKI CHESTER T ,  ELLIS-MONAGHAN JOHN J ,  FANG SUNFEI ,  LAVOIE CHRISTIAN ,  LUO ZHIJIONG ,  NAKOS JAMES S ,  STEEGEN AN L ,  WANN CLEMENT H

IPC: H01L21/8238 ,  H01L21/3205 ,  H01L21/44

CPC classification number: H01L21/28518 ,  H01L21/823814 ,  H01L21/823835

Abstract: A method of fabricating a complementary metal oxide semiconductor (CMOS) device, wherein the method comprises forming a first well region (103) in a semiconductor substrate (102) for accommodation of a first type semiconductor device (130); forming a second well region (104) in the semiconductor substrate (102) for accommodation of a second type semiconductor device (140); shielding the first type semiconductor device (130) with a mask (114); depositing a first metal layer (118) over the second type semiconductor device (140); performing a first salicide formation on the second type semiconductor device (140); removing the mask (114); depositing a second metal layer (123) over the first and second type semiconductor devices (130,140); and performing a second salicide formation on the first type semiconductor device (130). The method requires only one pattern level and it eliminates pattern overlay as it also simplifies the processes to form different suicide material over different devices.

Abstract translation: 一种制造互补金属氧化物半导体（CMOS）器件的方法，其中所述方法包括在半导体衬底（102）中形成用于容纳第一类型半导体器件（130）的第一阱区（103）; 在所述半导体衬底（102）中形成用于容纳第二类型半导体器件（140）的第二阱区（104）; 用掩模（114）屏蔽所述第一类型半导体器件（130）; 在所述第二类型半导体器件（140）上沉积第一金属层（118）; 在所述第二类型半导体器件（140）上执行第一自对准硅化物形成; 去除所述面罩（114）; 在第一和第二类型半导体器件（130,140）上沉积第二金属层（123）; 以及在所述第一类型半导体器件（130）上执行第二自对准硅化物形成。 该方法仅需要一个图案级别，并且消除图案覆盖，因为它也简化了在不同设备上形成不同的自杀材料的过程。

公开(公告)号：WO2005024906A2

公开(公告)日：2005-03-17

申请号：PCT/US2004027327

申请日：2004-08-20

Applicant: IBM ,  WANG YUN YU ,  STEEGEN AN L ,  KU VICTOR ,  WONG KWONG HON ,  LI YING ,  NARAYANAN VIJAY ,  CABRAL CYRIL JR ,  JAMISON PAUL

Inventor： STEEGEN AN L ,  KU VICTOR ,  WONG KWONG HON ,  LI YING ,  NARAYANAN VIJAY ,  CABRAL CYRIL JR ,  JAMISON PAUL

IPC: H01L21/28 ,  H01L21/336 ,  H01L29/49 ,  H01L

CPC classification number: H01L29/66545 ,  H01L21/28079 ,  H01L29/4958

Abstract: A structure and method for a metal replacement gate of a high performance device is provided. A sacrificial gate structure (260) is first formed on an etch stop layer (250) provided on a semiconductor substrate (240). A pair of spacers (400) is provided on sidewalls of the sacrificial gate structure (300). The sacrificial gate structure (300) is then removed, forming an opening (600). Subsequently, a metal gate (1000) including an first layer (700) of metal such as tungsten, a diffusion barrier (800) such as titanium nitride, and a second layer (900) of metal such as tungsten is formed in the opening (600) between the spacers (400).

Abstract translation: 提供了一种用于高性能器件的金属替换栅极的结构和方法。 牺牲栅极结构（260）首先形成在设置在半导体衬底（240）上的蚀刻停止层（250）上。 在牺牲栅极结构（300）的侧壁上设置一对间隔物（400）。 然后去除牺牲栅极结构（300），形成开口（600）。 接着，在开口部形成有包括诸如钨的金属的第一层（700），诸如氮化钛的扩散阻挡层（800）和诸如钨的金属的第二层（900）的金属栅极（1000） 600）之间。