公开(公告)号：EP1356507A4

公开(公告)日：2008-05-21

申请号：EP01996224

申请日：2001-12-30

Applicant: IBM

Inventor： GIEWONT KENNETH J ,  BRODSKY STEPHEN BRUCE ,  CABRAL CYRIL JR ,  DOMENICUCCI ANTHONY G ,  RANSOM CRAIG MITCHELL ,  WANG YUN-YU ,  WILDMAN HORATIO S ,  WONG KWONG HON

IPC: C23C14/06 ,  C23C14/34 ,  H01L21/28 ,  H01L21/285 ,  H01L29/423 ,  H01L29/49 ,  H01L29/78 ,  H01L21/44

CPC classification number: C23C14/0094 ,  C23C14/0641 ,  H01L21/28052 ,  H01L21/28518 ,  H01L21/2855

Abstract: A method is provided for forming a capping layer for a semiconductor structure including a silicide-forming metal (2) overlying silicon (1). According to the invention, a layer of nitride (51) is formed overlying the semiconductor structure and in contact with the silicide-forming metal (2). This layer is formed by sputtering form a target in an ambient characterized by a nitrogen flow less than about 45 sccm. The layer is therefore deficient in nitrogen, so that formation of an oxynitride at a native oxide layer (11) on the silicon is avoided and diffusion between the silicon (1) and the metal (2) is not inhibited.

公开(公告)号：JPH11135454A

公开(公告)日：1999-05-21

申请号：JP23405098

申请日：1998-08-20

Applicant: IBM ,  SIEMENS AG

Inventor： AJMERA ATUL C ,  DEHM CHRISTINE ,  DOMENICUCCI ANTHONY G ,  GIFFORD GEORGE G ,  LOH STEPHEN K ,  PARKS CHRISTOPHER ,  SARDESAI VIRAJI Y

IPC: H01L21/28 ,  H01L29/49

Abstract: PROBLEM TO BE SOLVED: To provide an improved method for forming a metallic silicide conductor in an integrated circuit. SOLUTION: A porous barrier is formed to prevent the thermal movement of silicon by enriching the grain boundary of a polysilicon layer 25 with nitrogen without forming an individual barrier layer. A reduction in the movement of the silicon prevents the agglomeration of the silicon in a metallic silicide layer formed on a policide gate/interconnection structure. The aggromelation of the silicon is a precedent advance phenomenon of a polycide inversion and hence effectively eliminates the polycide inversion passing through a lower oxide and damaging a device.

公开(公告)号：JPH11274104A

公开(公告)日：1999-10-08

申请号：JP2801699

申请日：1999-02-05

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレイション

Inventor： DOMENICUCCI ANTHONY G ,  LYNN M JINYAKKU ,  YUN YUU WAN ,  HOREESHIO S WILDMAN ,  KWON HON WON

IPC: H01L21/28 ,  H01L21/285 ,  H01L21/3205 ,  H01L21/321 ,  H01L21/768 ,  H01L23/52

CPC classification number: H01L21/76855 ,  H01L21/28518 ,  H01L21/28568 ,  H01L21/3212 ,  H01L21/76856 ,  H01L2221/1078

Abstract: PROBLEM TO BE SOLVED: To provide a conductive contact having an atomically flat interface, and its manufacturing method.
SOLUTION: A layer 12 containing cobalt and titanium is stuck on a silicon substrate 10 and the structure obtained is annealed at about 500 to 700°C under nitrogen containing atmosphere. A conductive material is stuck to the top of the annealed structure. A flat interface for preventing the conductive material from being diffused into a silicon substrate is formed. Then, with the use of this method a contact for an extremely small device or a shallow junction requited in a ULSI can be formed.
COPYRIGHT: (C)1999,JPO

Abstract translation: 要解决的问题：提供具有原子平面界面的导电接触及其制造方法。 解决方案：将含有钴和钛的层12粘贴在硅衬底10上，并且获得的结构在含氮气氛下在约500-700℃下退火。 导电材料粘附到退火结构的顶部。 形成用于防止导电材料扩散到硅衬底中的平坦界面。 然后，通过使用该方法，可以形成在ULSI中需要的极小的器件或浅结的接触。

公开(公告)号：JP2005026681A

公开(公告)日：2005-01-27

申请号：JP2004183839

申请日：2004-06-22

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： BEDELL STEPHEN W ,  CHEN HUAJIE ,  DOMENICUCCI ANTHONY G ,  FOGEL KEITH E ,  SADANA DEVENDRA K

IPC: H01L27/12 ,  H01L21/02 ,  H01L21/20 ,  H01L21/762

CPC classification number: H01L21/7624 ,  Y10S438/933 ,  Y10T428/12674

Abstract: PROBLEM TO BE SOLVED: To provide a method for manufacturing an SiGe-on-insulator substrate material substantially relaxed, of high quality, and capable of being used as a template for strained-silicon. SOLUTION: The SOI substrate having an ultra-thin top Si layer is used as the template for compressive strain SiGe growth. When an SiGe layer is relaxed at an enough temperature, the property of its dislocation movement is such that strain release defect moves down into the thin Si layer when an embedded oxide shows semi-viscosity behavior. The thin Si layer is consumed by oxidation of an interface of the thin Si with the embedded oxide. This can be performed by using inner oxidation at a high temperature. Therefore, the role of the original thin Si layer is to use the inner oxidation and subsequently to act as a sacrificial defective sink capable of being consumed during an SiGe alloy being relaxed. COPYRIGHT: (C)2005,JPO&NCIPI

Abstract translation: 要解决的问题：提供一种制造绝缘体上绝缘体衬底材料的方法，其基本上是松弛的，高质量的，并且能够用作应变硅的模板。 解决方案：使用具有超薄顶部Si层的SOI衬底作为压缩应变SiGe生长的模板。 当SiGe层在足够的温度下松弛时，其位错运动的性质使得当嵌入的氧化物显示半粘度行为时，应变释放缺陷向下移动到薄的Si层中。 薄的Si层被薄的Si与嵌入的氧化物的界面的氧化所消耗。 这可以通过在高温下使用内部氧化来进行。 因此，原始薄Si层的作用是使用内部氧化，随后作为在SiGe合金松弛期间能够消耗的牺牲缺陷槽。 版权所有（C）2005，JPO＆NCIPI

公开(公告)号：WO2011056313A3

公开(公告)日：2011-08-18

申请号：PCT/US2010049901

申请日：2010-09-23

Applicant: IBM ,  OZCAN AHMET S ,  LAVOIE CHRISTIAN ,  DOMENICUCCI ANTHONY G

Inventor： OZCAN AHMET S ,  LAVOIE CHRISTIAN ,  DOMENICUCCI ANTHONY G

IPC: H01L21/336 ,  H01L29/78

CPC classification number: H01L29/7833 ,  H01L21/28052 ,  H01L21/28114 ,  H01L29/42376 ,  H01L29/66507 ,  H01L29/6653 ,  H01L29/6659

Abstract: An integrated circuit is provided including a narrow gate stack having a width less than or equal to 65 nm, including a suicide region comprising Pt segregated in a region of the suicide away from the top surface of the suicide and towards an lower portion defined by a pulldown height of spacers on the sidewalls of the gate conductor. In a preferred embodiment, the spacers are pulled down prior to formation of the suicide. The suicide is first formed by a formation anneal, at a temperature in the range 250°C to 450°C. Subsequently, a segregation anneal at a temperature in the range 450°C to 550°C. The distribution of the Pt along the vertical length of the suicide layer has a peak Pt concentration within the segregated region, and the segregated Pt region has a width at half the peak Pt concentration that is less than 50% of the distance between the top surface of the suicide layer and the pulldown spacer height.

Abstract translation: 提供集成电路，其包括具有小于或等于65nm的宽度的窄栅极叠层，包括硅化物区域，该硅化物区域包括在远离硅化物顶表面的硅化物区域中偏析的Pt以及朝向由 在栅极导体的侧壁上的间隔物的下拉高度。 在一个优选实施例中，在形成硅化物之前将隔离物拉下。 该硅化物首先通过形成退火在250℃至450℃的温度下形成。 随后，在450℃至550℃的温度下进行偏析退火。 沿着硅化物层的垂直长度的Pt的分布在分离区域内具有峰值Pt浓度，并且分离的Pt区域具有在峰值Pt浓度的一半处的宽度，其小于顶部表面之间的距离的50％ 的硅化层和下拉间隔物高度。

公开(公告)号：WO2005067677A2

公开(公告)日：2005-07-28

申请号：PCT/US2005000072

申请日：2005-01-04

Applicant: IBM

Inventor： BEDELL STEPHEN W ,  CHAN KEVIN K ,  CHIDAMBARRAO DURESETI ,  CHRISTIANSEN SILKE H ,  CHU JACK O ,  DOMENICUCCI ANTHONY G ,  LEE KAM-LEUNG ,  MOCUTA ANDA C ,  OTT JOHN A ,  OUYANG QIQING C

IPC: H01L21/336 ,  H01L21/84 ,  H01L27/01 ,  H01L27/12 ,  H01L29/786

CPC classification number: H01L29/785 ,  H01L21/845 ,  H01L27/1211 ,  H01L29/66795

Abstract: A strained Fin Field Effect Transistor (FinFET) (and method for forming the same) includes a relaxed first material having a sidewall, and a strained second material formed on the sidewall of the first material. The relaxed first material and the strained second material form a fin of the FinFET.

Abstract translation: 应变Fin场效应晶体管（FinFET）（及其形成方法）包括具有侧壁的松弛的第一材料和形成在第一材料的侧壁上的应变的第二材料。 松弛的第一材料和应变的第二材料形成FinFET的鳍。

公开(公告)号：DE112010003344B4

公开(公告)日：2014-12-04

申请号：DE112010003344

申请日：2010-09-23

Applicant: IBM

Inventor： OZCAN AHMET S ,  LAVOIE CHRISTIAN ,  DOMENICUCCI ANTHONY G

IPC: H01L21/28 ,  H01L21/336 ,  H01L29/423 ,  H01L29/49 ,  H01L29/78

Abstract: Verfahren zur Herstellung einer Halbleiter-Vorrichtung, wobei dieses Verfahren die folgenden Schritte umfasst: – Bereitstellen eines Wafers umfassend, ein Halbleiter-Substrat, ein Gate-Stack auf dem Substrat, einschließlich einem Halbleiter-Gate-Leiter, mit einer Breite von weniger als oder gleich 65 nm, wobei jeweils ein einzelner dielektrischer Abstandshalter die Seitenwände des Gate-Leiters abdeckt, und die Abstandshalter dabei die obere Oberfläche des Gate-Leiters freigelegt lassen; – Herunter ziehen der dielektrischen Abstandshalter um einen oberen Abschnitt der Seitenwände des Halbleiter-Gate-Leiters bis zu einer Pull-down-Abstandshalter-Höhe freizulegen; – Bilden einer dünnen Metallschicht über dem Wafer mindestens über der freiliegenden oberen Oberfläche und dem oberen Abschnitt der Seitenwände des Halbleiter-Gate-Leiters, wobei die dünne Metallschicht Ni und Pt umfasst; – Durchführen eines Bildungs-Erhitzens, sodass die dünne Metallschicht mit dem Gate-Leiter reagiert, um eine monosilizide Schicht zu bilden; – Entfernen der nicht reagierten Anteile der dünnen Metallschicht; und – nach dem Entfernen dieser besagten nicht reagierten Anteile der dünnen Metallschicht, Durchführen eines Trennungs-Erhitzens bei einer höheren Temperatur als das Bildungs-Erhitzen, sodass mindestens 50% des Pt in einem abgetrennten Bereich in einer unteren Hälfte dieser besagten monosiliziden Schicht zwischen einer oberen Oberfläche der besagten monosiliziden Schicht und der besagten Pull-down-Abstandshalter-Höhe befindlich sind.

公开(公告)号：GB2487857A

公开(公告)日：2012-08-08

申请号：GB201205375

申请日：2010-09-23

Applicant: IBM

Inventor： OZCAN AHMET S ,  LAVOIE CHRISTIAN ,  DOMENICUCCI ANTHONY G

IPC: H01L21/28 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78

Abstract: An integrated circuit is provided including a narrow gate stack having a width less than or equal to 65 nm, including a suicide region comprising Pt segregated in a region of the suicide away from the top surface of the suicide and towards an lower portion defined by a pulldown height of spacers on the sidewalls of the gate conductor. In a preferred embodiment, the spacers are pulled down prior to formation of the suicide. The suicide is first formed by a formation anneal, at a temperature in the range 250°C to 450°C. Subsequently, a segregation anneal at a temperature in the range 450°C to 550°C. The distribution of the Pt along the vertical length of the suicide layer has a peak Pt concentration within the segregated region, and the segregated Pt region has a width at half the peak Pt concentration that is less than 50% of the distance between the top surface of the suicide layer and the pulldown spacer height.

公开(公告)号：GB2487857B

公开(公告)日：2014-05-07

申请号：GB201205375

申请日：2010-09-23

Applicant: IBM

Inventor： OZCAN AHMET S ,  LAVOIE CHRISTIAN ,  DOMENICUCCI ANTHONY G

IPC: H01L21/28 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78

Abstract: An integrated circuit is provided including a narrow gate stack having a width less than or equal to 65 nm, including a silicide region comprising Pt segregated in a region of the silicide away from the top surface of the silicide and towards an lower portion defined by a pulldown height of spacers on the sidewalls of the gate conductor. In a preferred embodiment, the spacers are pulled down prior to formation of the silicide. The silicide is first formed by a formation anneal, at a temperature in the range 250° C. to 450° C. Subsequently, a segregation anneal at a temperature in the range 450° C. to 550° C. The distribution of the Pt along the vertical length of the silicide layer has a peak Pt concentration within the segregated region, and the segregated Pt region has a width at half the peak Pt concentration that is less than 50% of the distance between the top surface of the silicide layer and the pulldown spacer height.

公开(公告)号：DE112010003344T5

公开(公告)日：2012-08-02

申请号：DE112010003344

申请日：2010-09-23

Applicant: IBM

Inventor： OZCAN AHMET S ,  LAVOIE CHRISTIAN ,  DOMENICUCCI ANTHONY G

IPC: H01L29/49 ,  H01L21/336 ,  H01L29/78

Abstract: Ein integrierter Schaltkreis wird bereitgestellt, mit einem schmalen Gate-Stack, mit einer Breite von weniger als oder gleich 65 nm, mit einem Silizid-Bereich, der einen von Pt abgetrennten Bereich des Silizid-Bereichs umfasst, beabstandet von der oberen Oberfläche des Silizids und getrennt von einem unteren Abschnitt, definiert durch eine Pull-down Höhe der Abstandshalter an den Seitenwänden des Gate-Leiters. In einer bevorzugten Ausführungsform werden die Abstandshalter vor der Bildung des Silizids heruntergezogen. Das Silizid wird zunächst durch ein Bildungs-Erhitzen bei einer Temperatur im Bereich von 250°C bis 450°C gebildet. Anschließend erfolgt ein Trennungs-Erhitzen bei einer Temperatur im Bereich von 450°C bis 550°C. Die Verteilung des Pt entlang der vertikalen Länge der Silizidschicht hat eine Pt-Spitzenkonzentration in dem abgetrennten Bereich, und der Pt abgetrennte Bereich hat eine Breite bei der halben Pt-Spitzenkonzentration von weniger als 50% des Abstandes zwischen der oberen Oberfläche der Silizidschicht und der Pull-down-Abstandshalter Höhe.