公开(公告)号：EP1356507A4

公开(公告)日：2008-05-21

申请号：EP01996224

申请日：2001-12-30

Applicant: IBM

Inventor： GIEWONT KENNETH J ,  BRODSKY STEPHEN BRUCE ,  CABRAL CYRIL JR ,  DOMENICUCCI ANTHONY G ,  RANSOM CRAIG MITCHELL ,  WANG YUN-YU ,  WILDMAN HORATIO S ,  WONG KWONG HON

IPC: C23C14/06 ,  C23C14/34 ,  H01L21/28 ,  H01L21/285 ,  H01L29/423 ,  H01L29/49 ,  H01L29/78 ,  H01L21/44

CPC classification number: C23C14/0094 ,  C23C14/0641 ,  H01L21/28052 ,  H01L21/28518 ,  H01L21/2855

Abstract: A method is provided for forming a capping layer for a semiconductor structure including a silicide-forming metal (2) overlying silicon (1). According to the invention, a layer of nitride (51) is formed overlying the semiconductor structure and in contact with the silicide-forming metal (2). This layer is formed by sputtering form a target in an ambient characterized by a nitrogen flow less than about 45 sccm. The layer is therefore deficient in nitrogen, so that formation of an oxynitride at a native oxide layer (11) on the silicon is avoided and diffusion between the silicon (1) and the metal (2) is not inhibited.

公开(公告)号：JP2001358229A

公开(公告)日：2001-12-26

申请号：JP2001134513

申请日：2001-05-01

Applicant: IBM ,  INFINEON TECHNOLOGIES CORP

Inventor： YUN YUU WAN ,  JAMMY RAJARAO ,  KIMBALL LEE J ,  KOTECKI DAVID E ,  LIAN JENNY ,  CHENTEIN RIN ,  MILLER JOHN A ,  NAGEL NICHOLAS ,  SHEN HUA ,  WILDMAN HORATIO S

IPC: H01L27/108 ,  H01L21/02 ,  H01L21/8242

Abstract: PROBLEM TO BE SOLVED: To provide a recessed electrode structure which interrupts the crystal grain boundary of an electrode and blocks the diffusion from the side wall. SOLUTION: The capacitor structure comprises an upper platinum electrode, a lower electrode and an insulator on the side wall of the electrode, and the lower electrode has a first recessed portion deposited to the insulator on its side wall and a second insulator portion deposited thereto.

公开(公告)号：JP2007243187A

公开(公告)日：2007-09-20

申请号：JP2007052225

申请日：2007-03-02

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： KEITH KWONG HON WONG ,  WILDMAN HORATIO S ,  YANG CHIH-CHAO ,  WANG YUN YU ,  CHRISTOPHER C PARKS

IPC: H01L21/28 ,  H01L21/288 ,  H01L21/3205 ,  H01L21/768 ,  H01L23/52

CPC classification number: H01L23/485 ,  H01L21/288 ,  H01L21/76843 ,  H01L21/76846 ,  H01L2924/0002 ,  H01L2924/00

Abstract: PROBLEM TO BE SOLVED: To provide new MOL metallurgy for avoiding a defect by using the MOL metallurgy of a prior art and its manufacturing method. SOLUTION: There is provided a semiconductor structure comprising a Co-containing liner arranged between an oxygen getter layer and a conductive material containing metal. The Co-containing liner, the oxygen getter layer, and the conductive material containing the metal form MOL metallurgy in which the Co-containing liner substitutes a conventional TiN liner. "Co-containing" means containing elemental Co only or containing at least one of elemental Co and P or B. The Co-containing liner is formed by an electroless deposition process in order to provide the Co-containing liner of fine step coatability using the inside of the contact opening of a high aspect ratio. COPYRIGHT: (C)2007,JPO&INPIT

Abstract translation: 要解决的问题：通过使用现有技术的MOL冶金及其制造方法来提供新的MOL冶金以避免缺陷。 解决方案：提供一种半导体结构，其包括布置在氧气吸气剂层和含有金属的导电材料之间的含Co衬里。 含Co的内衬，吸氧剂层和含有MOL冶金金属的导电材料，其中Co含量的衬垫取代了常规的TiN衬里。 “含Co”是指仅含有元素Co或含有元素Co和P或B中的至少一种。通过无电沉积方法形成含Co的内衬，以便使用 在高宽比的接触开口的内部。 版权所有（C）2007，JPO＆INPIT

公开(公告)号：JP2007150293A

公开(公告)日：2007-06-14

申请号：JP2006303411

申请日：2006-11-08

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： RIM KERN ,  ELLIS-MONAGHAN JOHN J ,  ROBERT J PURTELL ,  BRIAN J GREENE ,  CLEMENT H WANN ,  WILLIAM K HENSON ,  WILDMAN HORATIO S

IPC: H01L21/28

CPC classification number: H01L21/28518 ,  H01L21/823814 ,  H01L21/823835 ,  H01L21/84

Abstract: PROBLEM TO BE SOLVED: To provide a method for forming a semiconductor structure comprising different species of silicide or germanide positioned in different regions of the semiconductor structure.
SOLUTION: The different species of silicide or germanide is formed on a semiconductor layer and/or a conductor layer. By this invention, by utilizing combination of continuous accumulation of different metals and pattern formation, the different silicide or germanide are formed in the different regions of a semiconductor chip. This method includes a step for providing a Si-including layer or a Ge layer having at least a first region and a second region, a step for forming a first silicide or germanide in one of the first region and the second region, and a step for forming a second silicide or germanide having different composition from the first silicide or germanide in the other region not including the first silicide or germanide. The steps for forming the first and second silicide or germanide are performed continuously or with a single step.
COPYRIGHT: (C)2007,JPO&INPIT

Abstract translation: 要解决的问题：提供一种形成半导体结构的方法，所述半导体结构包括位于半导体结构的不同区域中的不同种类的硅化物或锗化物。 解决方案：在半导体层和/或导体层上形成不同种类的硅化物或锗化物。 通过本发明，通过利用不同金属的连续积累和图案形成的组合，在半导体芯片的不同区域中形成不同的硅化物或锗化物。 该方法包括提供具有至少第一区域和第二区域的含Si的层或Ge层的步骤，在第一区域和第二区域之一中形成第一硅化物或锗化物的步骤，以及步骤 用于在不包括第一硅化物或锗化锗的另一区域中形成具有不同组成的第二硅化物或锗化物与第一硅化物或锗化物。 用于形成第一和第二硅化物或锗化物的步骤连续地或单步进行。 版权所有（C）2007，JPO＆INPIT