公开(公告)号：AT170351T

公开(公告)日：1998-09-15

申请号：AT92480084

申请日：1992-06-22

Applicant: IBM

Inventor： BASSO CLAUDE ,  VERPLANKEN FABRICE ,  CALVIGNAC JEAN

IPC: G06F13/00 ,  H04L7/00 ,  H04L12/433 ,  H04L12/64 ,  H04L12/42

Abstract: A hub featuring several ports for attachment of stations to a LAN comprises concentration logic (14) for the handling of multiplexed incoming and outgoing Token-Ring and isochronous flows from and to the stations. The concentration logic comprises a clock recovery logic (42) from incoming Token-Ring packet data stream (40), for regeneration of Differential Manchester encoded data on output (400), and recovering of Token-Ring clock (401). A cycle framing generator (43) receives a 125 us synchronization clock (local or remote) from the hub backplane (402), and the Token-Ring clock (401), and generates control signals (403) to each of the 10 ports. Each port is made up of a port transmit interface (44), and a port receive interface (45). Data from a station hooked to the hub is input (404) to port receive interface (45). Token-Ring packet Differential Manchester encoded data are output (406) on to the next active port, and specifically to its port transmit interface, along with a recovered strobe clock (405), while ISO data are output (407) to a switch (46). The switch receives a hub local clock (412), which otherwise distributes on the whole concentration logic. isochronous traffic interchange with the hub backplane is ensured thru leads 410 and 411; inbetween ports or between ports and the hub is ensured thru leads 407 and 409 replicated for each port. Data to the station hooked to the hub is output (408) from port transmit interface (44). Differential Manchester encoded data are received (400) along with Token-Ring clock (401). Control signals are input (403). Isochronous data are received (409). Token-Ring packet Differential Manchester encoded data are finally output from the concentration logic (41).

公开(公告)号：CA2111075A1

公开(公告)日：1994-06-23

申请号：CA2111075

申请日：1993-12-09

Applicant: IBM

Inventor： BASSO CLAUDE ,  CALVIGNAC JEAN ,  VERPLANKEN FABRICE

IPC: H04L12/46 ,  H04L12/433 ,  H04L12/44 ,  H04L12/42

Abstract: TOKEN STAR SWITCH The invention includes a switch having N ports (N > 1), each port beingconnected to a Token-Ring physical segment, an additional port connected to an on-board processor, and a high-throughput port connected to a network of higher bandwidth than the Token Ring. The invention allows to route frames received at any one port to any or several ports, to begin the routing of the frames before they have been completely received at the input port, and to directly forward frames from input to output of the high badwidth port.

公开(公告)号：CA2111074A1

公开(公告)日：1994-06-23

申请号：CA2111074

申请日：1993-12-09

Applicant: IBM

Inventor： BASSO CLAUDE ,  CALVIGNAC JEAN ,  VERPLANKEN FABRICE

IPC: H04L12/433 ,  H04L12/56 ,  H04L12/42 ,  H04L12/66

Abstract: TOKEN STAR BRIDGE The invention includes a bridge having n ports (n > 1), each port being connected to a Token-Ring physical segment, each physical segment having one native Token-Ring workstation attached, said bridge comprising means for emulating to the workstations a single Token-Ring logical segment with a single Active Monitor and a single Ring Number. The invention allows to replace a MAC-per-port by a centralized function inside a centralized processor; the frame handling function, due to the fixed and limited configuration (same bridge Active Monitor seen by all connected stations), does not require a multi-port bridge function, but a simpler switch function between ports. Bridge clocking is also simplified, and a cost effectiveUTP retiming solution is presented.

公开(公告)号：CA2092628A1

公开(公告)日：1993-12-23

申请号：CA2092628

申请日：1993-03-12

Applicant: IBM

Inventor： BASSO CLAUDE ,  CALVIGNAC JEAN ,  VERPLANKEN FABRICE

IPC: G06F13/00 ,  H04L7/00 ,  H04L12/433 ,  H04L12/64 ,  H04L12/56 ,  H04L12/42 ,  H04J3/06

Abstract: A hub featuring several ports for attachment of stations to a LAN comprises concentration logic (14) for the handling of multiplexed incoming and outgoing Token-Ring and isochronous flows from and to the stations. The concentration logic comprises a clock recovery logic (42) from incoming Token-Ring packet data stream (40), for regeneration of Differential Manchester encoded data on output (400), and recovering of Token-Ring clock (401). A cycle framing generator (43) receives a 125 us synchronization clock (local or remote) from the hub backplane (402), and the Token-Ring clock (401), and generates control signals (403) to each of the 10 ports. Each port is made up of a port transmit interface (44), and a port receive interface (45). Data from a station hooked to the hub is input (404) to port receive interface (45). Token-Ring packet Differential Manchester encoded data are output (406) on to the next active port, and specifically to its port transmit interface, along with a recovered strobe clock (405), while ISO data are output (407) to a switch (46). The switch receives a hub local clock (412), which otherwise distributes on the whole concentration logic. isochronous traffic interchange with the hub backplane is ensured thru leads 410 and 411; inbetween ports or between ports and the hub is ensured thru leads 407 and 409 replicated for each port. Data to the station hooked to the hub is output (408) from port transmit interface (44). Differential Manchester encoded data are received (400) along with Token-Ring clock (401). Control signals are input (403). Isochronous data are received (409). Token-Ring packet Differential Manchester encoded data are finally output from the concentration logic (41).

公开(公告)号：DE3685587T2

公开(公告)日：1993-01-28

申请号：DE3685587

申请日：1986-08-27

Applicant: IBM

Inventor： CALVIGNAC JEAN ,  SECONDO PIERRE

IPC: H04L12/64 ,  H04L12/56 ,  H04L12/00

Abstract: Pseudo synchronous transportation mechanism to be used in a communication network comprising a plurality of nodes for exchanging non character coded information NCI and potentially character coded information on internode links in frames comprising circuit slots devoted to the transportation of character coded information, which are assigned to circuit users on the call basis under control of node management means 13. The slots are qualified by at least one qualification bit (Caq) which indicates when set to a first value (0) that the users are momentary active and when set to a second value (1) that the users are momentary inactive. The mechanism comprises in the nodes : - storing means (11, 12) in which queues of storing positions are assigned to the circuit users attached to the node, into which the circuit user information to be sent on the network internode links (l1, L2) and received from the network internode links are stored, - internode adapting means (14,15) which control the generation and the reception of the frames to and from each internode link operating under control of the node management means, which assign on the call basis , a set of at least one slot in the frames transported on the network link to a plurality of circuit users, and which comprise transmit and receive control means (24-T, 26-T, 20-R, 22-R, 28). The transmit control means causes the queues assigned to the plurality of local users to be sequentially scanned and read and the read information corresponding to momentary active users to be sent on the link during the assigned slot(s) of successive frames together with a qualification bit set to a first value. The receive control means causes the information received in the slot(s) assigned to the said plurality of users in successive frames to be written into the queues assigned to the users which are sequentially scanned, when the qualification bits are found equal to the first value.

公开(公告)号：DE3580481D1

公开(公告)日：1990-12-13

申请号：DE3580481

申请日：1985-08-13

Applicant: IBM

Inventor： CALVIGNAC JEAN ,  SECONDO PIERRE

IPC: H04L12/64 ,  H04Q11/04 ,  H04L12/54

Abstract: System to be used for dynamically allocating circuit slots in the frames which are used for exchanging bits between users connected to nodes of a communication network linked by means of medium links having transmit and receive interfaces, said frames being delimited by flags and divided into bit slots which may be devoted to synchronous circuit flow and to asynchronous packet flow. It comprises in each node means for changing the flags preceding at least one frame in which at least one slot is to be added or deleted to a value including a first number of delimiting bits and a second number of bits which are coded to indicate that slot(s) is (are) to be added or deleted and the corresponding slot number(s); means for sending call control packets which are propagated through the network nodes, comprising call control information , routing information and indicating the circuit user slot number(s) to be added or deleted on specified link interfaces, and means receiving the call control packets and the changed flags for adding or deleting circuit user slot(s) in the subsequent frames depending upon the flag value.

公开(公告)号：AT300763T

公开(公告)日：2005-08-15

申请号：AT02708513

申请日：2002-03-28

Applicant: IBM ,  CIT ALCATEL

Inventor： BARRI PETER ,  CALVIGNAC JEAN ,  HEDDES MARCO ,  LOGAN JOSEPH ,  NIEMEGEERS ALEX ,  VERPLANKEN FABRICE ,  VRANA MIROSLAV

IPC: G06F12/00 ,  G06F13/16 ,  G06F13/18

Abstract: A Network Processor (NP) includes a controller that allows maximum utilization of the memory. The controller includes a memory arbiter that monitors memory access requests from requesters in the NP and awards high priority requesters all the memory bandwidth requested per access to the memory. If the memory bandwidth requested by the high priority requester is less than the full memory bandwidth, the difference between the requested bandwidth and full memory bandwidth is assigned to lower priority requesters. By so doing every memory access utilizes the full memory bandwidth.

公开(公告)号：DE69226766T2

公开(公告)日：1999-04-15

申请号：DE69226766

申请日：1992-06-22

Applicant: IBM

Inventor： BASSO CLAUDE ,  VERPLANKEN FABRICE ,  CALVIGNAC JEAN

IPC: G06F13/00 ,  H04L7/00 ,  H04L12/433 ,  H04L12/64 ,  H04L12/42

Abstract: A hub featuring several ports for attachment of stations to a LAN comprises concentration logic (14) for the handling of multiplexed incoming and outgoing Token-Ring and isochronous flows from and to the stations. The concentration logic comprises a clock recovery logic (42) from incoming Token-Ring packet data stream (40), for regeneration of Differential Manchester encoded data on output (400), and recovering of Token-Ring clock (401). A cycle framing generator (43) receives a 125 us synchronization clock (local or remote) from the hub backplane (402), and the Token-Ring clock (401), and generates control signals (403) to each of the 10 ports. Each port is made up of a port transmit interface (44), and a port receive interface (45). Data from a station hooked to the hub is input (404) to port receive interface (45). Token-Ring packet Differential Manchester encoded data are output (406) on to the next active port, and specifically to its port transmit interface, along with a recovered strobe clock (405), while ISO data are output (407) to a switch (46). The switch receives a hub local clock (412), which otherwise distributes on the whole concentration logic. isochronous traffic interchange with the hub backplane is ensured thru leads 410 and 411; inbetween ports or between ports and the hub is ensured thru leads 407 and 409 replicated for each port. Data to the station hooked to the hub is output (408) from port transmit interface (44). Differential Manchester encoded data are received (400) along with Token-Ring clock (401). Control signals are input (403). Isochronous data are received (409). Token-Ring packet Differential Manchester encoded data are finally output from the concentration logic (41).

公开(公告)号：DE69021712D1

公开(公告)日：1995-09-21

申请号：DE69021712

申请日：1990-02-08

Applicant: IBM

Inventor： ALAIWAN HAISSAM ,  BASSO CLAUDE ,  CALVIGNAC JEAN ,  COMBES JACQUES ,  KERMAREC FRANCOIS ,  PAUPORTE ANDRE

IPC: G06F11/14 ,  G06F11/20 ,  G06F15/16

Abstract: A checkpointing mechanism implemented in a data processing system comprising a dual processor configuration gives the system a fault tolerance capability while minimizing the complexity of both the software and the hardware. The active and backup processors are coupled asynchronously with some hardware assist functions comprising a memory change detector which captures the memory changes in the memory of the active processor and a mirroring control circuit which causes the memory changes when committed by establish recovery point signals generated by the active processor to be dumped into the memory of the back up processor so that the backup processor can resume the operations of the active processor from the last established recovery point. The active and backup processors may each be connected to a dedicated memory and recovery point storing means, or to a memory including two dual sides shared by all the processors for storing data structures and recovery points.

公开(公告)号：DE69017198T2

公开(公告)日：1995-08-17

申请号：DE69017198

申请日：1990-05-15

Applicant: IBM

Inventor： CALVIGNAC JEAN ,  SAINT GEORGES ERIC ,  ORSATTI DANIEL ,  TOUBOL GILLES ,  VERPLANKEN FABRICE ,  NICOLAS FRANCOIS

IPC: H04Q3/52 ,  H04L12/64

Abstract: The hybrid packet and circuit switching system allows to merge the packet and circuit traffics from user interface modules 2-1 to 2-N on TDM bus 4-1 to 4N and to transfer packet information from one module to another module or exchange circuit information between modules. The circuit exchange or packet transfers are performed synchronously on the TDM busses in bursts of period T, with each burst comprising a fixed number of bytes. The bursts are switched by switch 1. There is a routing indication which is common to the packet and circuit bursts for controlling the switching of the bursts by the switch 1, which is performed by piggy backing the target module address for the circuit bursts as well as for the packet burst with the data bursts. The marking tables which are needed for the circuit burst allocation are located in the user interface modules.