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公开(公告)号：NZ232458A
公开(公告)日：1992-03-26
申请号：NZ23245890
申请日：1990-02-09
Applicant: IBM
Inventor： BLAKE ROBERT MARTIN , BOSSEN DOUGLAS CRAIG , CHEN CHIN-LONG , FIFIELD JOHN ATKINSON , KALTER HOWARD LEO , LO TIN-CHEE
Abstract: In a memory system comprising a plurality of memory units (10) each of which possesses unit-level error correction capabilities (20) and each of which are tied to a system level error correction function (30), memory reliability is enhanced by providing means for fixing the output of one of the memory units at a fixed value in response to the occurrence of an uncorrectable error in one of the memory units. This counter-intuitive approach to the generation of forced hard errors nonetheless enhances overall memory system reliability since it enables the employment of the complement/recomplement algorithm which depends upon the presence of reproducible errors for proper operation. Thus, chip level error correction systems, which are increasingly desirable at high packaging densities, are employed in a way which does not interfere with system level error correction methods.
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公开(公告)号：AU615373B2
公开(公告)日：1991-09-26
申请号：AU4939990
申请日：1990-02-09
Applicant: IBM
Inventor： BLAKE ROBERT MARTIN , BOSSEN DOUGLAS CRAIG , CHEN CHIN-LONG , FIFIELD JOHN ATKINSON , KALTER HOWARD LEO
Abstract: In a memory system comprising a plurality of memory units (10) each of which possesses unit-level error correction capabilities (20) and each of which are tied to a system level error correction function (30), memory reliability is enhanced by providing means (Fig. 2) for disabling the unit-level error correction capability, for example, in response to the occurrence of an uncorrectable error in one of the memory units. This counter-intuitive approach which disables an error correction function nonetheless enhances overall memory system reliability since it enables the employment of the complement/recomplement algorithm which depends upon the presence of reproducible errors for proper operation. Thus, chip level error correction systems, which are increasingly desirable at high packaging densities, are employed in a way which does not interfere with system level error correction methods.
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公开(公告)号：SG44390A1
公开(公告)日：1997-12-19
申请号：SG1996000087
申请日：1990-02-02
Applicant: IBM
Inventor： BLAKE ROBERT MARTIN , BOSSEN DOUGLAS CRAIG , CHEN CHIN-LONG , FIFIELD JOHN ATKINSON , KALTER HOWARD LEO , LO TIN-CHEE
Abstract: In a memory system comprising a plurality of memory units (10) each of which possesses unit-level error correction capabilities (20) and each of which are tied to a system level error correction function (30), memory reliability is enhanced by providing means for fixing the output of one of the memory units at a fixed value in response to the occurrence of an uncorrectable error in one of the memory units. This counter-intuitive approach to the generation of forced hard errors nonetheless enhances overall memory system reliability since it enables the employment of the complement/recomplement algorithm which depends upon the presence of reproducible errors for proper operation. Thus, chip level error correction systems, which are increasingly desirable at high packaging densities, are employed in a way which does not interfere with system level error correction methods.
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公开(公告)号：DE69026743T2
公开(公告)日：1996-11-07
申请号：DE69026743
申请日：1990-02-02
Applicant: IBM
Inventor： BLAKE ROBERT MARTIN , BOSSEN DOUGLAS CRAIG , CHEN CHIN-LONG , FIFIELD JOHN ATKINSON , KALTER HOWARD LEO , LO TIN-CHEE
Abstract: In a memory system comprising a plurality of memory units (10) each of which possesses unit-level error correction capabilities (20) and each of which are tied to a system level error correction function (30), memory reliability is enhanced by providing means for fixing the output of one of the memory units at a fixed value in response to the occurrence of an uncorrectable error in one of the memory units. This counter-intuitive approach to the generation of forced hard errors nonetheless enhances overall memory system reliability since it enables the employment of the complement/recomplement algorithm which depends upon the presence of reproducible errors for proper operation. Thus, chip level error correction systems, which are increasingly desirable at high packaging densities, are employed in a way which does not interfere with system level error correction methods.
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公开(公告)号：BR9001125A
公开(公告)日：1991-03-05
申请号：BR9001125
申请日：1990-03-09
Applicant: IBM
Inventor： BLAKE ROBERT MARTIN , BOSSEN DOUGLAS CRAIG , CHEN CHIN-LONG , FIFIELD JOHN ATKINSON , KALTER HOWARD LEO , LO TIN-CHEE
Abstract: In a memory system comprising a plurality of memory units (10) each of which possesses unit-level error correction capabilities (20) and each of which are tied to a system level error correction function (30), memory reliability is enhanced by providing means for fixing the output of one of the memory units at a fixed value in response to the occurrence of an uncorrectable error in one of the memory units. This counter-intuitive approach to the generation of forced hard errors nonetheless enhances overall memory system reliability since it enables the employment of the complement/recomplement algorithm which depends upon the presence of reproducible errors for proper operation. Thus, chip level error correction systems, which are increasingly desirable at high packaging densities, are employed in a way which does not interfere with system level error correction methods.
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Patent Agency Ranking
公开(公告)号：DE3380456D1
公开(公告)日：1989-09-28
申请号：DE3380456
申请日：1983-09-20
Applicant: IBM
Inventor： CHEN CHIN-LONG
IPC: G06F11/10
Abstract: @ A code is devised using BCH coding theory which corrects double bit failures and detects triple failures and packaging errors in a memory. The code is a shortened code in which both data and check bit columns have been removed from the parity check matrix. A decoding technique is used which splits the look-up tables used to reduce their size. The decoder (14) comprises a syndrome (S) generator (16), a first table (18) for determining a first Galois field element, vector (E1), which if not zero corresponds to the location of a first error, syndrome transformation and logical combination circuitry (20, 22) to determine a second vector (E2) which if not zero corresponds to a second error location, an uncorrectable error (UE) detector (36) and a package multibit error indicator (48). The vectors (E1) and (E2) are further decoded using Galois field to binary transformation tables (38, 42). A table (50) comprises syndrome patterns for triple bit failures within each package.
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公开(公告)号：CA1231456A
公开(公告)日：1988-01-12
申请号：CA488364
申请日：1985-08-08
Applicant: IBM
Inventor： ARLINGTON DAVID L , CHEN CHIN-LONG , EVANS EDWARD K
IPC: G06F11/10 , G06F12/16 , G11C11/401 , G11C29/00 , G11C29/42 , H03M13/00 , H03M13/03 , H03M13/19 , G06F11/00
Abstract: EXTENDED ERROR CORRECTION FOR PACKAGE ERROR CORRECTION CODES An extended error code particularly applicable to a code that can correct any number of errors in one sub-field but can only detect the existence of any number of errors in two sub-fields. If the initial pass of the data through the error correction code indicates an uncorrected error, the data is complemented and restored in the memory and then reread. The retrieved data is recomplemented and again passed through the error correction code. If an uncorrected error persists, then a bit-by-bit comparision is performed between the originally read data and the retrieved complemented data to isolate the hard fails in the memory. The bits in the sub-field associated with the hard fail are then sequentially changed and then the changed data word is passed through the error correction code. A wrong combination is detected by the error correction code. The sequential changing continues until the bits in the sub-field associated with the hard fail match the originally stored data, in which case the error correction code can correct the remaining errors in the remaining sub-fields.
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公开(公告)号：DE69021413T2
公开(公告)日：1996-03-21
申请号：DE69021413
申请日：1990-02-02
Applicant: IBM
Inventor： BLAKE ROBERT MARTIN , BOSSEN DOUGLAS CRAIG , CHEN CHIN-LONG , FIFIELD JOHN ATKINSON , KALTER HOWARD LEO
Abstract: In a memory system comprising a plurality of memory units (10) each of which possesses unit-level error correction capabilities (20) and each of which are tied to a system level error correction function (30), memory reliability is enhanced by providing means (Fig. 2) for disabling the unit-level error correction capability, for example, in response to the occurrence of an uncorrectable error in one of the memory units. This counter-intuitive approach which disables an error correction function nonetheless enhances overall memory system reliability since it enables the employment of the complement/recomplement algorithm which depends upon the presence of reproducible errors for proper operation. Thus, chip level error correction systems, which are increasingly desirable at high packaging densities, are employed in a way which does not interfere with system level error correction methods.
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公开(公告)号：DE69021413D1
公开(公告)日：1995-09-14
申请号：DE69021413
申请日：1990-02-02
Applicant: IBM
Inventor： BLAKE ROBERT MARTIN , BOSSEN DOUGLAS CRAIG , CHEN CHIN-LONG , FIFIELD JOHN ATKINSON , KALTER HOWARD LEO
Abstract: In a memory system comprising a plurality of memory units (10) each of which possesses unit-level error correction capabilities (20) and each of which are tied to a system level error correction function (30), memory reliability is enhanced by providing means (Fig. 2) for disabling the unit-level error correction capability, for example, in response to the occurrence of an uncorrectable error in one of the memory units. This counter-intuitive approach which disables an error correction function nonetheless enhances overall memory system reliability since it enables the employment of the complement/recomplement algorithm which depends upon the presence of reproducible errors for proper operation. Thus, chip level error correction systems, which are increasingly desirable at high packaging densities, are employed in a way which does not interfere with system level error correction methods.
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公开(公告)号：DE3882175D1
公开(公告)日：1993-08-12
申请号：DE3882175
申请日：1988-04-19
Applicant: IBM
Inventor： CHEN CHIN-LONG
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