中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

23 records (took 0.019 seconds)

    ELECTRONIC ASSEMBLY WITH FORCED CONVECTION COOLING
    11.
    发明专利
    ELECTRONIC ASSEMBLY WITH FORCED CONVECTION COOLING 未知

    公开(公告)号：DE3278616D1

    公开(公告)日：1988-07-07

    申请号：DE3278616

    申请日：1982-09-29

    Applicant: IBM

    Inventor： GARRETT MICHAEL JOHN ,  DAVIS MICHAEL IAN ,  WISEMAN JOHN ALAN

    IPC: H01L23/467 ,  H05K7/20

    Abstract: The electronic assembly has a support plate (10), on one surface of which are mounted side by side in the longitudinal direction several electronic equipment cabinets (11,12). Also on this surface there is at least one air distribution channel (21) extending longitudinally along the plate and a cooling fan (20). The latter (20) forces air along the air distribution channel (21) into the cabinets (11,12) to cool electrical components in them. The cross-section of each air distribution channel (21) may vary along its length so that different amounts of air are directed to the various components according to their cooling requirements. There may also be several secondary air distribution channels branching laterally from the main channel (21) and an arrangement for confining the air to flow into the secondary channels.

    16.
    发明专利
    未知

    公开(公告)号：DE2411963A1

    公开(公告)日：1974-11-14

    申请号：DE2411963

    申请日：1974-03-13

    Applicant: IBM

    Inventor： BROWN WENDELL WELLS ,  DAVIS MICHAEL IAN ,  PIPITONE RALPH MICHAEL

    IPC: G06F9/48 ,  G06F9/46 ,  G06F9/18

    Abstract: A data processor has multiple sets of hardware each of which is capable of autonomously controlling a common storage and common logical control circuits to execute a program. The hardware sets are allocated priority levels and are preferentially employed for handling interrupt service requests. Any hardware set which is interrupted in processing by a higher priority input request retains its processing status and resumes processing when control of the common elements is returned to it. Apparatus is included for addressing the set associated with a different priority level than the current level so that this different level can be preempted for another task. The presence of an interrupted program in the preempted level can be detected and its critical status stored for restoration after completion of the preempting program.

    Data processing system with address translator arrangement
    18.
    发明专利
    Data processing system with address translator arrangement 未知

    公开(公告)号：CH617523A5

    公开(公告)日：1980-05-30

    申请号：CH532977

    申请日：1977-04-28

    Applicant: IBM

    Inventor： BIRNEY RICHARD EUGENE ,  DAVIS MICHAEL IAN ,  GRAYBIEL LYNN ALLAN ,  KAHN SAMUEL ,  OSBORNE WILLIAM STEESE ,  HOOD ROBERT ALLEN ,  BOURKE DONALL GERRAID

    IPC: G06F12/02 ,  G06F9/36

    Abstract: In a data processing system with translation of the logic addresses, predetermined in the programs, into the physical addresses necessary for memory access, special devices are provided by means of which flexible allocation of address areas for various categories of information or various types of programs is possible. The address translator arrangement has a separate translator unit (stack 0... stack 7) for each address area. In addition, an arrangement (20...35) for storing various address keys for various categories of information and for outputting one of these keys each on the basis of present memory access control signals is provided. One of the translator units is then in each case selected with the aid of the output address key by means of an additional selection device (40). This makes it possible to obtain different physical addresses from the same logic address during the translation, dependently on which category of information is to be accessed at the time and dependently on the address key in each case allocated to the category of information.

    ADDRESS KEY REGISTER LOAD/STORE INSTRUCTION SYSTEMS
    19.
    发明专利
    ADDRESS KEY REGISTER LOAD/STORE INSTRUCTION SYSTEMS 未知

    公开(公告)号：AU2474777A

    公开(公告)日：1978-11-09

    申请号：AU2474777

    申请日：1977-05-02

    Applicant: IBM

    Inventor： BIRNEY RICHARD EUGENE ,  DAVIS MICHAEL IAN ,  GRAYBIEL LYNN ALLAN ,  HOOD ROBERT ALLEN ,  OSBORNE WILLIAM STEESE ,  KAHN SAMUEL

    IPC: G06F9/312 ,  G06F11/00 ,  G06F12/14 ,  G06F13/12 ,  G06F21/24 ,  G06F13/06

    Abstract: The disclosure describes instruction operated controls for loading or storing address key values into or from one or more address key register sections in a key-register-controlled addressing system. The controls load or store one or all key register sections of an address key register (AKR) in a processor from or to a word in either a main memory or a general purpose register (GPR). Both the load or store controls are operated by the same instruction format, in which one field indicates whether the operation is to be a load or store of the designated AKR section(s). Another field designates one AKR section, or all AKR sections, which are to be loaded or stored. A still further field designates whether the operation is to be from or to main memory or a GPR. The disclosure provides circuits which operate with microcode to perform these operations.

    20.
    发明专利
    未知

    公开(公告)号：DE2756762A1

    公开(公告)日：1978-07-06

    申请号：DE2756762

    申请日：1977-12-20

    Applicant: IBM

    Inventor： DAVIS MICHAEL IAN ,  HOOD ROBERT ALLEN ,  MAYES GARY WAYNE

    IPC: G06F9/305 ,  G06F9/34 ,  G06F12/04 ,  G06F9/06 ,  G06F13/06

    Abstract: A method of accessing variable-length bit fields in the memory of an electronic data processing system irrespective of the relationship between the boundaries of addressable elements within said memory and the start and end of the bit fields comprising the operations of: setting the initial values of a base register within said system to contain a representation of a base address of an addressable element; setting the initial values of a shift register within said system to contain a representation of the offset in said memory of the beginning of a particular bit field from said base address; combining the contents of said base and offset registers in such a way as to provide a representation of the position in said memory of the first bit of said particular bit field; create a single instruction that contains a representation of the length of said particular bit field. (Machine-translation by Google Translate, not legally binding)

Patent Agency Ranking