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    11.
    发明专利
    未知

    公开(公告)号：DE69126292D1

    公开(公告)日：1997-07-03

    申请号：DE69126292

    申请日：1991-10-28

    Applicant: IBM

    Inventor： DHONG SANG HOO ,  HWANG WEI ,  TAIRA YOICHI

    IPC: G11C11/407 ,  G11C11/408 ,  H01L21/76 ,  H01L21/8242 ,  H01L27/10 ,  H01L27/108 ,  H03K5/02 ,  G11C8/00

    Abstract: A wordline driver circuit is shown for a DRAM, the circuit comprising a PMOS transistor structure (58) having one contact coupled to a wordline (60), a second contact coupled to a negative voltage supply and a gate coupled to a control input, the transistor having an N-well (64) about the gate, first and second contacts. An isolating structure (66) is positioned about the N-well (64) to enable it to be a separately controlled from surrounding N-well structures (64). Pulse circuits (52) are coupled to the transistor (58) for applying, when activated, a potential that enables the wordline (60) to transition to a more negative potential. A bias circuit is also provided for biasing the N-well (64) at a first potential and a second lower potential, the second lower potential applied when the pulse circuits (52) are activated. As a result, body effects in the PMOS transistor (58) are minimized while at the same time enabling a boost potential to be applied to the wordline (60).

    WORDLINE VOLTAGE BOOSTING CIRCUITS FOR COMPLEMENTARY MOSFET DYNAMIC MEMORIES
    12.
    发明专利
    WORDLINE VOLTAGE BOOSTING CIRCUITS FOR COMPLEMENTARY MOSFET DYNAMIC MEMORIES 未知

    公开(公告)号：AU625691B2

    公开(公告)日：1992-07-16

    申请号：AU5216990

    申请日：1990-03-26

    Applicant: IBM

    Inventor： DHONG SANG HOO ,  HWANG WEI ,  LU NICKY CHAU-CHUN

    IPC: G11C11/407 ,  G11C11/408 ,  H03K5/02 ,  G11C5/14

    Abstract: An improved wordline boost clock circuit that can be used in high speed DRAM circuits requires only one boost capacitor (42) and discharges the wordlines faster, thus improving the DRAM access time. The basic feature of the clock circuit is in the floating gate structure of the NMOS device which drives the load to negative during the boosting. In a first embodiment of the clock (Fig. 2), the gate of a first device (24) is connected to a first node (26) through a second device (28). A second node (30), connected to a wordline, is discharged through the first (24) and a third (32) device when a third node (36) is high with a fourth node (38) low. After a sufficient discharge of the second node (30), the fourth node (38) is pulled to VDD turning the second device (28) on and a fourth device (40) off. The first (NMOS) transistor (24) has its gate and drain connected together and forms a diode. When a boost capacitor (42) pulls the first node (26) down to negative, the first device (24) stays completely off because of its diode configuration and the second node (30) is pulled to negative through the third device (32). In a second embodiment (Fig. 3), a first device (24) is connected between a boost capacitor and a second node (30). The load is discharged through a third device (32) with a fourth device (40) on but a first (24) and second device (28) off. After a sufficient discharge of the load, a fourth device (40) is turned off but a second device (28) is turned on, making the third device (32) a diode. When a fifth node (74) is pulled to ground, the second node 30 is pulled down to negative with the first device (24) on. In the second embodiment circuit the load discharges through only one NMOS device (32) and consequently discharges faster than the circuit of the first embodiment.

    RY MOSFET DYNAMIC MEMORIES
    13.
    发明专利
    RY MOSFET DYNAMIC MEMORIES 未知

    公开(公告)号：AU5216990A

    公开(公告)日：1990-11-01

    申请号：AU5216990

    申请日：1990-03-26

    Applicant: IBM

    Inventor： DHONG SANG HOO ,  HWANG WEI ,  LU NICKY CHAU-CHUN

    IPC: G11C11/407 ,  G11C11/408 ,  H03K5/02 ,  G11C5/14

    Abstract: An improved wordline boost clock circuit that can be used in high speed DRAM circuits requires only one boost capacitor (42) and discharges the wordlines faster, thus improving the DRAM access time. The basic feature of the clock circuit is in the floating gate structure of the NMOS device which drives the load to negative during the boosting. In a first embodiment of the clock (Fig. 2), the gate of a first device (24) is connected to a first node (26) through a second device (28). A second node (30), connected to a wordline, is discharged through the first (24) and a third (32) device when a third node (36) is high with a fourth node (38) low. After a sufficient discharge of the second node (30), the fourth node (38) is pulled to VDD turning the second device (28) on and a fourth device (40) off. The first (NMOS) transistor (24) has its gate and drain connected together and forms a diode. When a boost capacitor (42) pulls the first node (26) down to negative, the first device (24) stays completely off because of its diode configuration and the second node (30) is pulled to negative through the third device (32). In a second embodiment (Fig. 3), a first device (24) is connected between a boost capacitor and a second node (30). The load is discharged through a third device (32) with a fourth device (40) on but a first (24) and second device (28) off. After a sufficient discharge of the load, a fourth device (40) is turned off but a second device (28) is turned on, making the third device (32) a diode. When a fifth node (74) is pulled to ground, the second node 30 is pulled down to negative with the first device (24) on. In the second embodiment circuit the load discharges through only one NMOS device (32) and consequently discharges faster than the circuit of the first embodiment.

    Voltage boosting circuits for dynamic memories
    15.
    发明专利
    Voltage boosting circuits for dynamic memories 未知

    公开(公告)号：HK203796A

    公开(公告)日：1996-11-15

    申请号：HK203796

    申请日：1996-11-07

    Applicant: IBM

    Inventor： DHONG SANG HOO ,  HWANG WEI ,  LU NICKY CHAU-CHUN

    IPC: G11C11/408 ,  H03K5/02 ,  G11C11/407

    Abstract: An improved wordline boost clock circuit that can be used in high speed DRAM circuits requires only one boost capacitor (42) and discharges the wordlines faster, thus improving the DRAM access time. The basic feature of the clock circuit is in the floating gate structure of the NMOS device which drives the load to negative during the boosting. In a first embodiment of the clock (Fig. 2), the gate of a first device (24) is connected to a first node (26) through a second device (28). A second node (30), connected to a wordline, is discharged through the first (24) and a third (32) device when a third node (36) is high with a fourth node (38) low. After a sufficient discharge of the second node (30), the fourth node (38) is pulled to VDD turning the second device (28) on and a fourth device (40) off. The first (NMOS) transistor (24) has its gate and drain connected together and forms a diode. When a boost capacitor (42) pulls the first node (26) down to negative, the first device (24) stays completely off because of its diode configuration and the second node (30) is pulled to negative through the third device (32). In a second embodiment (Fig. 3), a first device (24) is connected between a boost capacitor and a second node (30). The load is discharged through a third device (32) with a fourth device (40) on but a first (24) and second device (28) off. After a sufficient discharge of the load, a fourth device (40) is turned off but a second device (28) is turned on, making the third device (32) a diode. When a fifth node (74) is pulled to ground, the second node 30 is pulled down to negative with the first device (24) on. In the second embodiment circuit the load discharges through only one NMOS device (32) and consequently discharges faster than the circuit of the first embodiment.

    17.
    发明专利
    未知

    公开(公告)号：DE602006003869D1

    公开(公告)日：2009-01-08

    申请号：DE602006003869

    申请日：2006-01-25

    Applicant: IBM

    Inventor： TAKAHASHI OSAMU ,  HOFSTEE HARM PETER ,  FLACHS BRIAN KING ,  DHONG SANG HOO

    IPC: G06F13/16

    Abstract: A system for a processor with memory with combined line and word access is presented. A system performs narrow read/write memory accesses and wide read/write memory accesses to the same memory bank using multiplexers and latches to direct data. The system processes 16 byte load/sore requests using a narrow read/write memory access and also processes 128 byte DMA and instruction fetch requests using a wide read/write memory access. During DMA requests, the system writes/reads sixteen DMA operations to memory on one instruction cycle. By doing this, the memory is available to process load/store or instruction fetch requests during fifteen other instruction cycles.

    18.
    发明专利
    未知

    公开(公告)号：DE69938911D1

    公开(公告)日：2008-07-31

    申请号：DE69938911

    申请日：1999-02-26

    Applicant: IBM

    Inventor： DHONG SANG HOO ,  SILBERMAN JOEL ABRAHAM

    IPC: G06F9/32 ,  G06F9/38

    Abstract: A processor and method of fetching an instruction from a memory are disclosed. According to the method of the present invention, a plurality of target addresses are determined utilizing a plurality of previously fetched instructions, and a sequential address is determined utilizing a last of the plurality of previously fetched instructions. Concurrently with the determination of the target addresses and the sequential address, a select signal specifying one of the plurality of target addresses or the sequential address is generated. The select signal is used to select one of the plurality of target addresses or the sequential address as a memory request address. The memory request address is then transmitted from the processor to the memory so that the memory will supply at least one instruction to the processor. By generating the target addresses and sequential address concurrently with the generation of the selection signal, instruction fetch latency is reduced.

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