中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

27 records (took 0.036 seconds)

    11.
    发明专利
    未知

    公开(公告)号：BR9001125A

    公开(公告)日：1991-03-05

    申请号：BR9001125

    申请日：1990-03-09

    Applicant: IBM

    Inventor： BLAKE ROBERT MARTIN ,  BOSSEN DOUGLAS CRAIG ,  CHEN CHIN-LONG ,  FIFIELD JOHN ATKINSON ,  KALTER HOWARD LEO ,  LO TIN-CHEE

    IPC: G06F12/16 ,  G06F11/10 ,  G11C29/00

    Abstract: In a memory system comprising a plurality of memory units (10) each of which possesses unit-level error correction capabilities (20) and each of which are tied to a system level error correction function (30), memory reliability is enhanced by providing means for fixing the output of one of the memory units at a fixed value in response to the occurrence of an uncorrectable error in one of the memory units. This counter-intuitive approach to the generation of forced hard errors nonetheless enhances overall memory system reliability since it enables the employment of the complement/recomplement algorithm which depends upon the presence of reproducible errors for proper operation. Thus, chip level error correction systems, which are increasingly desirable at high packaging densities, are employed in a way which does not interfere with system level error correction methods.

    12.
    发明专利
    未知

    公开(公告)号：DE69120333T2

    公开(公告)日：1997-01-23

    申请号：DE69120333

    申请日：1991-03-01

    Applicant: IBM

    Inventor： FIFIELD JOHN ATKINSON

    IPC: G06F11/10 ,  G06F12/16 ,  G11C11/401 ,  G11C29/00 ,  G11C29/42

    Abstract: An interlocked on-chip ECC system for DRAMs wherein performance degradations due to on-chip ECC are minimized without compromising accurate ECC operations. Several interlocks used in the system insure that the data thereto is valid at certain critical stages. The remainder of the system is allowed to run on a self-timed basis to maximize speed. For example, a dummy data line (DDL) is used to signal the ECC (30) when data from the DRAM arrays (10) is valid during a fetch operation; the same dummy data line (DDL) also signals the DRAM arrays (10) when the data from the ECC (30) is valid during a write-back operation.

    14.
    发明专利
    未知

    公开(公告)号：DE69021413T2

    公开(公告)日：1996-03-21

    申请号：DE69021413

    申请日：1990-02-02

    Applicant: IBM

    Inventor： BLAKE ROBERT MARTIN ,  BOSSEN DOUGLAS CRAIG ,  CHEN CHIN-LONG ,  FIFIELD JOHN ATKINSON ,  KALTER HOWARD LEO

    IPC: G06F12/16 ,  G06F11/10 ,  G06F11/00

    Abstract: In a memory system comprising a plurality of memory units (10) each of which possesses unit-level error correction capabilities (20) and each of which are tied to a system level error correction function (30), memory reliability is enhanced by providing means (Fig. 2) for disabling the unit-level error correction capability, for example, in response to the occurrence of an uncorrectable error in one of the memory units. This counter-intuitive approach which disables an error correction function nonetheless enhances overall memory system reliability since it enables the employment of the complement/recomplement algorithm which depends upon the presence of reproducible errors for proper operation. Thus, chip level error correction systems, which are increasingly desirable at high packaging densities, are employed in a way which does not interfere with system level error correction methods.

    15.
    发明专利
    未知

    公开(公告)号：DE69021413D1

    公开(公告)日：1995-09-14

    申请号：DE69021413

    申请日：1990-02-02

    Applicant: IBM

    Inventor： BLAKE ROBERT MARTIN ,  BOSSEN DOUGLAS CRAIG ,  CHEN CHIN-LONG ,  FIFIELD JOHN ATKINSON ,  KALTER HOWARD LEO

    IPC: G06F12/16 ,  G06F11/10 ,  G06F11/00

    Abstract: In a memory system comprising a plurality of memory units (10) each of which possesses unit-level error correction capabilities (20) and each of which are tied to a system level error correction function (30), memory reliability is enhanced by providing means (Fig. 2) for disabling the unit-level error correction capability, for example, in response to the occurrence of an uncorrectable error in one of the memory units. This counter-intuitive approach which disables an error correction function nonetheless enhances overall memory system reliability since it enables the employment of the complement/recomplement algorithm which depends upon the presence of reproducible errors for proper operation. Thus, chip level error correction systems, which are increasingly desirable at high packaging densities, are employed in a way which does not interfere with system level error correction methods.

    16.
    发明专利
    未知

    公开(公告)号：DE69012395T2

    公开(公告)日：1995-03-30

    申请号：DE69012395

    申请日：1990-03-13

    Applicant: IBM

    Inventor： FIFIELD JOHN ATKINSON ,  KALTER HOWARD LEO

    IPC: G11C11/401 ,  G11C7/18 ,  G11C11/4097 ,  G11C7/00 ,  G11C11/409

    Abstract: This invention relates to semiconductor memories and includes a sense amplifier architecture in which sensed data bit lines (e.g. BL2, BL2 min ) are electrically isolated and shielded from their immediately adjacent active neighbors by utilization of non-selected bit lines (e.g. BL1, BL1 min and/or BL3, BL3 min ) as an AC ground bus. In its simplest embodiment, shielded bit line (SBL) architecture includes two pairs of opposed bit lines (BL1, BL2; BL1 min , BL2 min )associated with a common sense amplifier (10). One of each of the bit line pairs is multiplexed into the sense amplifier and the other unselected bit line pair is clamped to AC ground to shield the selected bit line pair from all dynamic line-to-line coupling.

    Fault tolerant computer memory systems and components employing dual level error correction and detection with disablement feature
    18.
    发明专利
    Fault tolerant computer memory systems and components employing dual level error correction and detection with disablement feature 未知

    公开(公告)号：SG46485A1

    公开(公告)日：1998-02-20

    申请号：SG1996005030

    申请日：1990-02-02

    Applicant: IBM

    Inventor： BLAKE ROBERT MARTIN ,  BOSSEN DOUGLAS CRAIG ,  CHEN CHIN-LONG ,  FIFIELD JOHN ATKINSON ,  KALTER HOWARD LEO

    IPC: G06F11/10 ,  G06F12/16 ,  G06F11/00

    Abstract: In a memory system comprising a plurality of memory units (10) each of which possesses unit-level error correction capabilities (20) and each of which are tied to a system level error correction function (30), memory reliability is enhanced by providing means (Fig. 2) for disabling the unit-level error correction capability, for example, in response to the occurrence of an uncorrectable error in one of the memory units. This counter-intuitive approach which disables an error correction function nonetheless enhances overall memory system reliability since it enables the employment of the complement/recomplement algorithm which depends upon the presence of reproducible errors for proper operation. Thus, chip level error correction systems, which are increasingly desirable at high packaging densities, are employed in a way which does not interfere with system level error correction methods.

    FAULT TOLERANT MEMORY
    20.
    发明专利
    FAULT TOLERANT MEMORY 未知

    公开(公告)号：NZ232466A

    公开(公告)日：1992-08-26

    申请号：NZ23246690

    申请日：1990-02-09

    Applicant: IBM

    Inventor： BLAKE ROBERT MARTIN ,  BOSSEN DOUGLAS CRAIG ,  CHEN CHIN-LONG ,  FIFIELD JOHN ATKINSON ,  KALTER HOWARD LEO

    IPC: G06F11/10 ,  G06F12/16 ,  G06F11/16 ,  G11C29/00

    Abstract: In a memory system comprising a plurality of memory units (10) each of which possesses unit-level error correction capabilities (20) and each of which are tied to a system level error correction function (30), memory reliability is enhanced by providing means (Fig. 2) for disabling the unit-level error correction capability, for example, in response to the occurrence of an uncorrectable error in one of the memory units. This counter-intuitive approach which disables an error correction function nonetheless enhances overall memory system reliability since it enables the employment of the complement/recomplement algorithm which depends upon the presence of reproducible errors for proper operation. Thus, chip level error correction systems, which are increasingly desirable at high packaging densities, are employed in a way which does not interfere with system level error correction methods.

Patent Agency Ranking