公开(公告)号：MX2023013910A

公开(公告)日：2023-12-08

申请号：MX2023013910

申请日：2022-05-31

Applicant: IBM

Inventor： HELLER LISA ,  SLEGEL TIMOTHY ,  BORNTRAEGER CHRISTIAN ,  GIAMEI BRUCE ,  OSISEK DAMIAN ,  GAERTNER UTE ,  YOST CHRISTINE ,  TZORTZATOS ELPIDA

IPC: G06F12/1009 ,  G06F12/02 ,  G06F12/0891 ,  G06F12/1027 ,  G06F12/14

Abstract: Se proporciona una instrucción para llevar a cabo una operación de reinicio de protección de traducción de dirección cuando se ejecuta. Ejecutar la instrucción incluye determinar, por medio de un procesador, que se va a reiniciar un bit de protección de traducción de dirección en una entrada de tabla de traducción especificada asociada con un bloque de almacenamiento. Con base en la determinación de que se va a reiniciar el bit de protección de traducción de dirección, ejecutar la instrucción incluye reiniciar el bit de protección de traducción de dirección para desactivar la protección contra escritura para el bloque de almacenamiento. El reinicio no espera una acción por uno o más de otros procesadores del entorno de cómputo.

公开(公告)号：GB2496328B

公开(公告)日：2015-07-08

申请号：GB201300337

申请日：2011-05-19

Applicant: IBM

Inventor： KOEHLER THOMAS ,  GAERTNER UTE

IPC: G06F12/10 ,  G06F12/0855 ,  G06F12/1027

公开(公告)号：DE19848742C2

公开(公告)日：2002-05-02

申请号：DE19848742

申请日：1998-10-22

Applicant: IBM

Inventor： GAERTNER UTE ,  GETZLAFF KLAUS J ,  PFEFFER ERWIN ,  TAST HANS-WERNER

IPC: G06F9/38 ,  G06F9/28

Abstract: A system and method for register renaming and allocation in an out-of-order processing system which allows the use of a minimum number of physical registers is described. A link list allows concatenation of a physical register representing a certain instance of the corresponding logical register to the physical register representing the next instance of the same logical register. By adding and removing links in this link list, it is possible to manage the assignment of physical registers to logical registers dynamically. Both the physical registers representing speculative instances and the physical registers representing in-order instances are administrated together. This is done by means of an in-order list, which indicates the physical registers that actually represent the architected state of the machine.

公开(公告)号：AU2022287210A1

公开(公告)日：2023-11-02

申请号：AU2022287210

申请日：2022-05-31

Applicant: IBM

Inventor： GIAMEI BRUCE ,  SLEGEL TIMOTHY ,  BORNTRAEGER CHRISTIAN ,  OSISEK DAMIAN ,  HELLER LISA ,  GAERTNER UTE ,  YOST CHRISTINE ,  TZORTZATOS ELPIDA

IPC: G06F12/1009 ,  G06F12/1027 ,  G06F12/14

Abstract: An instruction is provided to perform a reset address translation protection operation when executed. Executing the instruction includes determining, by a processor, that an address translation protection bit in a specified translation table entry associated with a storage block is to be reset. Based on determining that the address translation protection bit is to be reset, executing the instruction includes resetting the address translation protection bit to deactivate write protection for the storage block. The resetting is absent waiting for an action by one or more other processors of the computing environment.

公开(公告)号：DE69831282D1

公开(公告)日：2005-09-29

申请号：DE69831282

申请日：1998-02-05

Applicant: IBM

Inventor： GAERTNER UTE ,  GETZLAFF DIPL-ING ,  KOEHLER DIPL-ING ,  PFEFFER DIPL-ING

IPC: G06F9/30 ,  G06F9/38

Abstract: The invention relates to the area of register renaming and allocation in superscalar computer systems. When a multitude of instructions in the instruction stream reads from or writes to a certain logical register, said logical register will have to be represented by a multitude of physical registers. Therefore, there have to exist several physical rename registers per logical register. The oldest one of said rename registers defines the architected state of the computer system, the in-order state. The invention provides a method for administration of the various register instances. Both the registers representing the in-order state and the various rename instances are kept in one common circular buffer. There exist two pointers per logical register: The first one, the in-order pointer, points to the register that represents the in-order state, the second one, the rename pointer, points to the most recent rename instance.

公开(公告)号：DE19929051A1

公开(公告)日：2000-02-24

申请号：DE19929051

申请日：1999-06-25

Applicant: IBM

Inventor： GAERTNER UTE ,  GETZLAFF KLAUS J ,  LAUB OLIVER ,  PFEFFER ERWIN

IPC: G06F9/30 ,  G06F9/302 ,  G06F9/312 ,  G06F9/38

Abstract: The data processing system is designed to handle a mixed sequence of 64 and 32 bit long instructions by using an identification process based around the register contents. The 32 bit instruction is located and is copied into a target register . The copy source and register numbers are listed in table form.

公开(公告)号：DE19929050A1

公开(公告)日：2000-02-24

申请号：DE19929050

申请日：1999-06-25

Applicant: IBM

Inventor： GAERTNER UTE ,  HAESS JUERGEN ,  LAUB OLIVER ,  MAURER EBERHARD ,  PFEFFER ERWIN

IPC: G06F9/32 ,  G06F9/38

Abstract: The data processor has a condition code buffer (10) and counter (26) and a number of execution units (22,24). The buffer is configured as a matrix and the data is stored in mirrored form in the buffer. In order to determine if the code for the following operation is valid a comparison (28) is made between values.

公开(公告)号：DE19848742A1

公开(公告)日：1999-06-24

申请号：DE19848742

申请日：1998-10-22

Applicant: IBM

Inventor： GAERTNER UTE ,  GETZLAFF KLAUS J ,  PFEFFER ERWIN ,  TAST HANS-WERNER

IPC: G06F9/38 ,  G06F9/28

Abstract: The system includes an arrangement of physical storage registers which form instances of logical registers. A sequence list associates each logical register with a corresponding physical register, and a connection list associates a physical register which forms an instance of a logical register, to a physical register of an earlier, preceding instance of the same logical register, to form a chain of physical registers according to a sequence of instructions. An Independent claim is provided for a method associating physical registers with logical registers.

公开(公告)号：CA3217151A1

公开(公告)日：2022-12-08

申请号：CA3217151

申请日：2022-05-31

Applicant: IBM

Inventor： GIAMEI BRUCE ,  SLEGEL TIMOTHY ,  BORNTRAEGER CHRISTIAN ,  OSISEK DAMIAN ,  HELLER LISA ,  GAERTNER UTE ,  YOST CHRISTINE ,  TZORTZATOS ELPIDA

IPC: G06F12/1009 ,  G06F12/1027

Abstract: An instruction is provided to perform a reset address translation protection operation when executed. Executing the instruction includes determining, by a processor, that an address translation protection bit in a specified translation table entry associated with a storage block is to be reset. Based on determining that the address translation protection bit is to be reset, executing the instruction includes resetting the address translation protection bit to deactivate write protection for the storage block. The resetting is absent waiting for an action by one or more other processors of the computing environment.

公开(公告)号：DE112011100982T5

公开(公告)日：2013-05-02

申请号：DE112011100982

申请日：2011-05-19

Applicant: IBM

Inventor： KOEHLER THOMAS ,  GAERTNER UTE

IPC: G06F12/10 ,  G06F12/08 ,  G06F12/0855 ,  G06F12/1027

Abstract: Ein verbessertes Verfahren zur Adressumsetzung in einem System mit einer Adressumsetzungseinheit (1), eine Umsetzungseinrichtung (26) aufweisend, die so konfiguriert ist, dass sie einen Umsetzungstabellen-Abrufvorgang ausführt, und einen Adressumsetzpuffer (28), der so konfiguriert ist, dass er einen Suchvorgang zur schnellen Adressumsetzung ausführt, wird offenbart. Das Verfahren weist auf: Ausführen des Suchvorgangs im Adressumsetzpuffer (28) auf der Grundlage einer ersten Umsetzungsanforderung als aktuelle Umsetzungsanforderung, wobei im Falle eines Treffers eine entsprechende absolute Adresse als Umsetzungsergebnis für die erste Umsetzungsanforderung an einen entsprechenden Anforderer (LSU, COP, IFU) rückübertragen wird; Aktivieren der Umsetzungseinrichtung (26) zum Ausführen von mindestens einem Umsetzungstabellen-Abrufvorgang, falls die aktuelle Umsetzungsanforderung keinen Eintrag im Adressumsetzpuffer (28) als Treffer liefert; wobei die Umsetzungseinrichtung (26) in inaktivem Zustand auf die Rückübertragung von Daten aus dem mindestens einen Umsetzungstabellen-Abrufvorgang wartet, Melden des inaktiven Zustands der Umsetzungseinrichtung (26) als Bedingung „Suche bei Fehlschlag” und Annehmen einer aktuell anstehenden Umsetzungsanforderung als zweite Umsetzungsanforderung, wobei auf der Grundlage der zweiten Umsetzungsanforderung eine Sequenz „Suche bei Fehlschlag” im Adressumsetzpuffer (28) ausgeführt wird.