公开(公告)号：GB2581082A

公开(公告)日：2020-08-05

申请号：GB202005861

申请日：2018-11-01

Applicant: IBM

Inventor： TAKASHI ANDO ,  CHIH-CHAO YANG ,  BENJAMIN BRIGGS ,  MICHAEL RIZZOLO ,  LAWRENCE CLEVENGER

IPC: H01L45/00

Abstract: A method is presented for forming a semiconductor device. The method includes depositing an insulating layer over a semiconductor substrate, etching the insulating layer to form a plurality of trenches for receiving a first conducting material, forming a resistive switching memory element over at least one trench of the plurality of trenches, the resistive switching memory element having a conducting cap formed thereon, and depositing a dielectric cap over the trenches. The method further includes etching portions of the insulating layer to expose a section of the dielectric cap formed over the resistive switching memory element, etching the exposed section of the dielectric cap to expose the conducting cap of the resistive switching memory element, and forming a barrier layer in direct contact with the exposed section of the conducting cap.

公开(公告)号：GB2555269A

公开(公告)日：2018-04-25

申请号：GB201718865

申请日：2016-05-27

Applicant: IBM

Inventor： BENJAMIN DAVID BRIGGS ,  MICHAEL RIZZOLO ,  LAWRENCE CLEVENGER ,  KOICHI MOTOYAMA

IPC: H01L23/528 ,  H01L21/768 ,  H01L23/522 ,  H01L23/532

Abstract: After forming a trench opening (52) including narrow trench portions (52A) spaced apart by wide trench portions (52B) and forming a stack of a first diffusion barrier layer (62) and a first liner layer (64) on sidewalls and a bottom surface of the trench opening (52), a reflow process is performed to fill the narrow trench portions (52A) but not the wide trench portions (52B) with a first conductive material layer (66). A stack of a second diffusion barrier layer (72) and a second liner layer (74) is formed on portions of the first liner layer (64) and ends of the first conductive material layer (66) exposed by the wide trench portions (52B). A second conductive material layer (76) is deposited to fill the wide trench portions (52B). Portions of the second diffusion barrier layer (72) and the second liner layer (74) located between the first conductive material layer (66) and the second conductive material layer (76) act as vertical blocking boundaries to prevent the electromigration of metal atoms.

公开(公告)号：GB2608771A

公开(公告)日：2023-01-11

申请号：GB202215360

申请日：2021-02-12

Applicant: IBM

Inventor： TIMOTHY MATTHEW PHILIP ,  LAWRENCE CLEVENGER ,  KEVIN BREW

IPC: G11C13/00

Abstract: A phase change memory device is provided. The phase change memory device includes a phase change memory material within an electrically insulating wall, a first heater terminal in the electrically insulating wall, and two read terminals in the electrically insulating wall.

公开(公告)号：GB2601100B

公开(公告)日：2022-08-31

申请号：GB202204077

申请日：2020-09-08

Applicant: IBM

Inventor： MICHAEL RIZZOLO ,  NICHOLAS ANTHONY LANZILLO ,  BENJAMIN DAVID BRIGGS ,  LAWRENCE CLEVENGER

IPC: G11C11/16 ,  H01L27/22 ,  H01L43/12

Abstract: Encapsulation topography-assisted techniques for forming self-aligned top contacts in MRAM devices are provided. In one aspect, a method for forming an MRAM device includes: forming MTJs on interconnects embedded in a first dielectric; depositing an encapsulation layer over the MTJs; burying the MTJs in a second dielectric; patterning a trench in the second dielectric over the MTJs exposing the encapsulation layer over tops of the MTJs which creates a topography at the trench bottom; forming a metal line in the trench over the topography; recessing the metal line which breaks up the metal line into segments separated by exposed peaks of the encapsulation layer; recessing the exposed peaks of the encapsulation layer to form recesses at the tops of the MTJs; and forming self-aligned contacts in the recesses. An MRAM device is also provided.

公开(公告)号：GB2600667A

公开(公告)日：2022-05-04

申请号：GB202202974

申请日：2020-08-06

Applicant: IBM

Inventor： CHANRO PARK ,  NICHOLAS ANTHONY LANZILLO ,  CHRISTOPHER PENNY ,  LAWRENCE CLEVENGER ,  BALASUBRAMANIAN PRANATHARTHI HARAN

IPC: H01L21/60 ,  H01L21/768 ,  H01L23/528

Abstract: An interconnect structure (100) includes an interlayer dielectric (ILD) (112) having a cavity (122) extending therethrough along a first direction. A first electrically conductive strip (110) is formed on a substrate (102) and within the cavity (122). The first electrically conductive strip (110) extends along the first direction and across an upper surface of the substrate (102). A second electrically conductive strip (118) is on an upper surface of the ILD (112) and extends along a second direction opposite the first direction. A fully aligned via (FAV) (124) extends between the first and second electrically conductive strips (110, 118) such that all sides of the FAV (124) are co-planar with opposing sides of the first electrically conductive strip (110) and opposing sides of the second electrically conductive strip (118) thereby providing a FAV (124) that is fully aligned with the first electrically conductive strip (110) and the second electrically conductive strip (118).

公开(公告)号：GB2576466B

公开(公告)日：2022-01-26

申请号：GB201917751

申请日：2018-05-29

Applicant: IBM

Inventor： BENJAMIN DAVID BRIGGS ,  LEIGH ANNE CLEVENGER ,  MICHAEL RIZZOLO ,  MARYAM ASHOORI ,  SPYRIDON SKORDAS ,  LAWRENCE CLEVENGER ,  JUSTIN CANAPERI

IPC: G06F3/041

Abstract: A system for a touch screen interface that includes a coating including a plurality of a touch activated microchips; and a projector for projecting a light image onto the coating that is applied to a touch screen substrate. The system also includes an image calibrator that calibrates touch activated microchips in the coating to features of the light image projected onto the coating. The system further includes a receiver for receiving signal from the touch activated microchips when said feature of the light image is activated.