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    11.
    发明专利
    未知

    公开(公告)号：BR9402596A

    公开(公告)日：1995-06-13

    申请号：BR9402596

    申请日：1994-06-29

    Applicant: IBM

    Inventor： GALAND CLAUDE ,  LEBIZAY GERALD ,  MAUDUIT DANIEL ,  MUNIER JEAN-MARIE ,  PAUPORTE ANDRE ,  SAINT-GEORGES ERIC ,  SPAGNOL VICTOR

    IPC: H04L29/06 ,  H04L12/56

    Abstract: A high performance data packet buffering method and a programmable data communication adapter for high speed packet transmission networks are disclosed. The line adapter includes programmable processing means, for receiving and transmitting data packets of fixed or variable length. This system is characterized in that it comprises means for buffering (132) said data packets, means for identifying said buffering means and said data packets in said buffering means, means for queueing (Figure 15) in storing means (131) said identifying means in a single instruction, means for dequeueing (Figure 16) from said storing (131) means said identifying means in another single instruction , means for releasing said buffering means, Each instruction comprises up to three operations executed in parallel by said processing means : an arithmetical and logical (ALU) operation on said identifying means, a memory operation on said storing means, and a sequence operation.

    12.
    发明专利
    未知

    公开(公告)号：DE68918275T2

    公开(公告)日：1995-03-30

    申请号：DE68918275

    申请日：1989-06-29

    Applicant: IBM

    Inventor： LEBIZAY GERALD ,  DEMANGE MICHEL ,  VEDRENNE ALAIN ,  MILEWSKI ANDRZEJ

    IPC: H04Q3/00 ,  H04L12/56

    Abstract: A 3-stage switching system is provided for generating, i.e. finding, reserving and setting, path from one switch entrance port (1) to at least one switch exit port (transmit side) for asynchronously received and buffered data cells. While an Nth cell is being transferred, control means (36) generate a control word including the switch exit port address for cell (N+1)th to be subsequently transferred. Said control word is used to find and reserve a path through the switch on a stage-by-stage basis, and then set said path, if any, using a fed back acknowledgement. The (N+1)th cell path generation is performed during cell N transfer, on a cycle stealing basis.

    Method and Apparatus to Speed Up the Path Selection in a Packet Switching Network
    13.
    发明专利
    Method and Apparatus to Speed Up the Path Selection in a Packet Switching Network 未知

    公开(公告)号：CA2123449A1

    公开(公告)日：1995-01-31

    申请号：CA2123449

    申请日：1994-05-12

    Applicant: IBM

    Inventor： ALFONSI JEAN-PIERRE ,  GALAND CLAUDE ,  LEBIZAY GERALD ,  MAUREL OLIVIER

    IPC: H04L12/56

    Abstract: Currently, the routing algorithms compute all the available paths in the network, from the source node to the destination node before to select the optimal route. No assumption is made on the network topology and the route computation is often time and resource consuming. Some paths which are calculated are not acceptable due to the particular geographical configuration of the network. In the real world, large transport networks are not fully meshed. The present invention is based on the observation that networks are usually built around a hierarchical structure. A set of nodes, interconnected by high throughput lines, are used to build a 'Backbone' (401) with a high degree of meshing to allow the redundancy and reliability required by the user. The other nodes or 'local' nodes (404) are attached to one or several backbone nodes. It is the network designer responsibility, at the configuration time to define for each node what is its attribution : backbone (402) or local node (404). The list of the node attributions appears in the topology table (306) and is updated each time a node is added to or dropped from the network. The routing algorithm can take advantage of the particular network topology to drastically reduce the complexity of paths computation. For a given connection, only a limited number of nodes are eligible and are taken in account by the algorithm in the optimal route search. The object of the invention is to split the network in backbone and local nodes to speed up the path selection.

    TIME-SPACE-TIME SWITCHING NETWORK USING A CLOSED-LOOP LINK
    15.
    发明专利
    TIME-SPACE-TIME SWITCHING NETWORK USING A CLOSED-LOOP LINK 未知

    公开(公告)号：CA1210841A

    公开(公告)日：1986-09-02

    申请号：CA440704

    申请日：1983-11-08

    Applicant: IBM

    Inventor： BOISSEAU MARC ,  BORIE JEAN C ,  CROISIER ALAIN ,  DEMANGE MICHEL ,  LEBIZAY GERALD ,  ROSSI JEAN-PIERRE P

    IPC: H04Q11/04 ,  H04Q11/06

    Abstract: A TIME-SPACE-TIME SWITCHING NETWORK USING A CLOSED-LOOP LINK A switching network for selectively connecting at least one input time-division channel on an input link (IL) to at least one output time-division channel on an output link (OL). The network is organized around a closed-loop link on which circulates a multiplex message carrying 512 time-division exchange channels. The input and output links are respectively multiplexed onto an input multiplex link (IML) and an output multiplex link (OML) which are coupled to the closed loop by a switching module (SM). Each switching module comprises an input buffer (IB), an output buffer (OB) and a local buffer (LB) the addressing of which is selectively controlled by a time slot counter (CTR) or a corresponding pointer memory. So-called "broadcast" connections coupling one input channel to several output channels, and "in-cast" connections coupling several input channels to one output channel, can be established. Each of these connections uses only one exchange channel.

    19.
    发明专利
    未知

    公开(公告)号：DE2405401A1

    公开(公告)日：1974-09-19

    申请号：DE2405401

    申请日：1974-02-05

    Applicant: IBM

    Inventor： COUDER ALAIN ,  LEBIZAY GERALD

    IPC: G06F13/00 ,  H04Q11/04

    Abstract: Two-way links communication capability between time-division multiplexed subsystems is provided via dual time division address and data busses correlated by a recirculating memory having sections respectively associated with the address busses. Addresses on the address busses are recognized by the individual subsystems and further decoded to gate data to and from the busses data according to time slots assigned to terminal devices in the subsystems. The dual bus arrangement provides a full-duplex link in the sense that there is simultaneous communication via the two data busses, one each way.

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