公开(公告)号：DE69737172D1

公开(公告)日：2007-02-15

申请号：DE69737172

申请日：1997-07-15

Applicant: SIEMENS AG ,  IBM

Inventor： HAUE MANFRED ,  LEVY MAX G ,  NASTASI VICTOR RAY

IPC: H01L21/8242 ,  H01L29/78 ,  H01L21/306 ,  H01L21/336 ,  H01L21/8234 ,  H01L27/088 ,  H01L27/108 ,  H01L29/423

Abstract: A Field Effect Transistor (FET) and a method of forming FETs on a silicon wafer. First, trenches are formed in a surface of the silicon wafer. An ONO layer is formed on the surface, lining the trenches. Potassium is diffused along the ONO layer. Part of the ONO layer is removed to expose the wafer surface with the ONO layer remaining in the trenches. Gate oxide is formed on the exposed wafer surface. Finally, FET gates are formed on the gate oxide. Preferably, potassium is introduced during Chem-Mech polish when the trenches are filled with polysilicon. A slurry containing KOH is used to polish the polysilicon and the potassium diffuses from the slurry along the ONO layer. After chem-Mech polish, the poly in the trenches is recessed by Reactive Ion Etching (RIE) it below the wafer surface. Optionally, after RIE, the wafer may be dipped in a KOH solution. Next, an oxide collar is formed along the ONO layer in the trenches above the recessed polysilicon. The recesses are filled by a second layer of polysilicon that is Chem-Mech polished with the same slurry to remove polysilicon from the wafer surface. The polished polysilicon may be Reactive Ion etched until it is essentially coplanar with the wafer surface. The resulting FET has thicker gate oxide along its sides than in the center of its channel.

公开(公告)号：DE69807621T2

公开(公告)日：2003-11-27

申请号：DE69807621

申请日：1998-06-26

Applicant: INFINEON TECHNOLOGIES AG ,  IBM

Inventor： LEVY MAX G ,  FIEGL BERNHARD ,  BERGNER WOLFGANG ,  GOTH GEORGE R ,  PARRIES PAUL ,  SENDELBACH MATTHEW J ,  WANG TING-HAO ,  WILLE WILLIAM C ,  WITTMANN JUERGEN

IPC: H01L21/302 ,  H01L21/304 ,  H01L21/306 ,  H01L21/3105 ,  H01L21/76 ,  H01L21/321

Abstract: A method for preventing CMP-induced (chemical-mechanical polish) damage to a substrate disposed below a pad nitride layer of a mesa. The pad nitride layer is disposed below a conformally deposited dielectric layer. The dielectric layer is disposed below a conformally deposited polysilicon layer. The method includes planarizing the polysilicon layer down to at least a surface of the dielectric layer using the CMP to expose a first region of the dielectric layer. The method further includes etching partially through the first region of the dielectric layer using first etch parameters. The first etch parameters include an etchant source gas that is substantially selective to the pad nitride layer to prevent the pad nitride layer from being etched through even in the presence of a CMP defect. Additionally, there is also included removing the polysilicon layer after the etching partially through the first region of the dielectric layer.

公开(公告)号：DE112010004612B4

公开(公告)日：2014-02-13

申请号：DE112010004612

申请日：2010-09-30

Applicant: IBM

Inventor： ELLIS-MONAGHAN JOHN J ,  LEVY MAX G ,  PHELPS RICHARD A ,  BOTULA ALAN B ,  JOSEPH ALVIN J ,  SLINKMAN JAMES A

IPC: H01L27/12 ,  G06F17/50 ,  H01L21/265 ,  H01L21/84

Abstract: Halbleiterstruktur (100), aufweisend: ein Halbleitersubstrat (110) eines bestimmten Leitungstyps mit einer ersten Fläche (114) und einer zweiten Fläche (115) oberhalb der ersten Fläche (114), wobei das Halbleitersubstrat (110) Folgendes aufweist: einen der ersten Fläche (114) benachbarten ersten Teil (101), der einen Dotanden (111) des bestimmten Leitungstyps in einer ersten Konzentration aufweist; und einen zweiten Teil (102), der sich von dem ersten Teil (101) bis zu der zweiten Fläche (115) erstreckt und Folgendes aufweist: eine Vielzahl Mikrokavitäten (122); und in einer zweiten Konzentration, die größer als die erste Konzentration ist, irgendeines des Folgenden: einen gleichen Dotanden (111) wie in dem ersten Teil (101), einen von dem ersten Teil (101) verschiedenen Dotanden (112), wobei der verschiedene Dotand (112) den bestimmten Leitungstyp aufweist, und eine Kombination des gleichen Dotanden (111) und des verschiedenen Dotanden (112); und eine der zweiten Fläche (115) benachbarte Isolatorschicht (120).

公开(公告)号：DE69738059T2

公开(公告)日：2008-05-21

申请号：DE69738059

申请日：1997-07-15

Applicant: SIEMENS AG ,  IBM

Inventor： HAUF MANFRED ,  LEVY MAX G ,  NASTASI VICTOR RAY

IPC: H01L21/76 ,  H01L21/763 ,  H01L21/3105 ,  H01L21/8234 ,  H01L21/8242 ,  H01L27/088 ,  H01L27/108 ,  H01L29/78

Abstract: An FET isolated on either side by a trench. The FET has a dielectric layer in the isolating trench along at least one side. The dielectric layer which may be an ONO layer has an oxidation catalyst diffused into it. The oxidation catalyst may be potassium. Gate oxide along the side of the FET in close proximity to the ONO layer is thicker than gate oxide between both sides.

公开(公告)号：DE69712138T2

公开(公告)日：2003-01-30

申请号：DE69712138

申请日：1997-07-14

Applicant: IBM ,  SIEMENS AG

Inventor： HAUF MANFRED ,  LEVY MAX G ,  NASTASI VICTOR RAY

IPC: H01L27/08 ,  H01L21/8242 ,  H01L27/108 ,  H01L27/088

Abstract: An integrated circuit with FETs having an essentially uniform gate oxide thickness and FETs having gate oxide thickness enhanced along the sides. FETs with enhanced gate oxide have an ONO layer (126) diffused with Potassium in close proximity to the enhanced (thicker) oxide, and, as a result, have a slightly higher Vt and much more attenuated soft turn on.

公开(公告)号：GB2487860B

公开(公告)日：2014-08-27

申请号：GB201206521

申请日：2010-09-30

Applicant: IBM

Inventor： BOTULA ALAN B ,  ELLIS-MONAGHAN JOHN ,  JOSEPH ALVIN ,  LEVY MAX G ,  PHELPS RICHARD A ,  SLINKMAN JAMES A

IPC: H01L27/12

Abstract: Disclosed is semiconductor structure with an insulator layer on a semiconductor substrate and a device layer is on the insulator layer. The substrate is doped with a relatively low dose of a dopant having a given conductivity type such that it has a relatively high resistivity. Additionally, a portion of the semiconductor substrate immediately adjacent to the insulator layer can be doped with a slightly higher dose of the same dopant, a different dopant having the same conductivity type or a combination thereof. Optionally, micro-cavities are created within this same portion so as to balance out any increase in conductivity with a corresponding increase in resistivity. Increasing the dopant concentration at the semiconductor substrate-insulator layer interface raises the threshold voltage (Vt) of any resulting parasitic capacitors and, thereby reduces harmonic behavior. Also disclosed herein are embodiments of a method and a design structure for such a semiconductor structure.

公开(公告)号：DE69738059D1

公开(公告)日：2007-10-11

申请号：DE69738059

申请日：1997-07-15

Applicant: SIEMENS AG ,  IBM

Inventor： HAUF MANFRED ,  LEVY MAX G ,  NASTASI VICTOR RAY

IPC: H01L21/76 ,  H01L21/763 ,  H01L21/3105 ,  H01L21/8234 ,  H01L21/8242 ,  H01L27/088 ,  H01L27/108 ,  H01L29/78

Abstract: An FET isolated on either side by a trench. The FET has a dielectric layer in the isolating trench along at least one side. The dielectric layer which may be an ONO layer has an oxidation catalyst diffused into it. The oxidation catalyst may be potassium. Gate oxide along the side of the FET in close proximity to the ONO layer is thicker than gate oxide between both sides.

公开(公告)号：DE69802607T2

公开(公告)日：2002-07-25

申请号：DE69802607

申请日：1998-03-12

Applicant: SIEMENS AG ,  IBM

Inventor： FIEGL BERNHARD ,  GLASHAUSER WALTER ,  LEVY MAX G ,  NASTASI VICTOR R

IPC: H01L21/76 ,  H01L21/304 ,  H01L21/3105 ,  H01L21/762

公开(公告)号：DE69712138D1

公开(公告)日：2002-05-29

申请号：DE69712138

申请日：1997-07-14

Applicant: IBM ,  SIEMENS AG

Inventor： HAUF MANFRED ,  LEVY MAX G ,  NASTASI VICTOR RAY

IPC: H01L27/08 ,  H01L21/8242 ,  H01L27/108 ,  H01L27/088

Abstract: An integrated circuit with FETs having an essentially uniform gate oxide thickness and FETs having gate oxide thickness enhanced along the sides. FETs with enhanced gate oxide have an ONO layer (126) diffused with Potassium in close proximity to the enhanced (thicker) oxide, and, as a result, have a slightly higher Vt and much more attenuated soft turn on.

公开(公告)号：SG50865A1

公开(公告)日：1998-07-20

申请号：SG1997002418

申请日：1997-07-09

Applicant: IBM ,  SIEMENS AG

Inventor： HAUF MANFRED ,  LEVY MAX G ,  NASTASI VICTOR RAY

IPC: H01L27/08 ,  H01L21/8242 ,  H01L27/108 ,  H01L27/105

Abstract: An integrated circuit with FETs having an essentially uniform gate oxide thickness and FETs having gate oxide thickness enhanced along the sides. FETs with enhanced gate oxide have an ONO layer (126) diffused with Potassium in close proximity to the enhanced (thicker) oxide, and, as a result, have a slightly higher Vt and much more attenuated soft turn on.