公开(公告)号：DE112004000745T5

公开(公告)日：2006-06-08

申请号：DE112004000745

申请日：2004-05-06

Applicant: INFINEON TECHNOLOGIES AG ,  IBM

Inventor： BEINTNER JOCHEN ,  LI YUJUN ,  MOUMEN NAIM ,  WRSCHKA PORSHIA SHANE

IPC: H01L21/28 ,  H01L29/423 ,  H01L21/265 ,  H01L21/336 ,  H01L29/49 ,  H01L29/78 ,  H01L29/786

Abstract: The structure and method of forming a notched gate MOSFET disclosed herein addresses such problems as device reliability. A gate dielectric (e.g. gate oxide) is formed on the surface of an active area on the semiconductor substrate, preferably defined by an isolation trench region. A layer of polysilicon is then deposited on the gate dielectric. This step is followed by depositing a layer of silicon germanium) (SiGe). The sidewalls of the polysilicon layer are then laterally etched, selective to the SiGe layer to create a notched gate conductor structure, with the SiGe layer being broader than the underlying polysilicon layer. Sidewall spacers are preferably formed on sidewalls of the SiGe layer and the polysilicon layer. A silicide layer is preferably formed as a self-aligned silicide from a polysilicon layer deposited over the SiGe layer, to reduce resistance of the gate conductor. One or more other processing steps (e.g. source and drain implants, extension implants, and pocket lightly doped drain (LDD) implants), gate conductor stack doping, and silicidation are preferably performed in completing the transistor.

公开(公告)号：AT539448T

公开(公告)日：2012-01-15

申请号：AT04780833

申请日：2004-08-12

Applicant: IBM

Inventor： WANG GENG ,  MCSTAY KEVIN ,  WEYBRIGHT MARY ,  LI YUJUN ,  CHIDAMBARRAO DURESETI

IPC: H01L21/8234 ,  H01L21/265 ,  H01L21/336 ,  H01L21/8242 ,  H01L29/10 ,  H01L29/78

Abstract: A method of formation of a deep trench vertical transistor is provided. A deep trench with a sidewall in a doped semiconductor substrate is formed. The semiconductor substrate includes a counterdoped drain region in the surface thereof and a channel alongside the sidewall. The drain region has a top level and a bottom level. A counterdoped source region is formed in the substrate juxtaposed with the sidewall below the channel. A gate oxide layer is formed on the sidewalls of the trench juxtaposed with a gate conductor. Perform the step of recessing the gate conductor below the bottom level of the drain region followed by performing angled ion implantation at an angle theta+delta with respect to vertical of a counterdopant into the channel below the source region and performing angled ion implantation at an angle theta with respect to vertical of a dopant into the channel below the source.

公开(公告)号：DE10233234A1

公开(公告)日：2003-04-17

申请号：DE10233234

申请日：2002-07-22

Applicant: INFINEON TECHNOLOGIES CORP ,  IBM

Inventor： YE QIUYI ,  TONTI WILLIAM ,  LI YUJUN ,  MANDELMAN JACK A

IPC: H01L21/336 ,  H01L21/8238 ,  H01L29/78

Abstract: A MOSFET having a new source/drain (S/D) structure is particularly adapted to smaller feature sizes of modern CMOS technology. The S/D conductors are located on the shallow trench isolation (STI) to achieve low junction leakage and low junction capacitance. The S/D junction depth is defined by an STI etch step (according to a first method of making the MOSFET) or a silicon etch step (according to a second method of making the MOSFET). By controlling the etch depth, a very shallow junction depth is achieved. There is a low variation of gate length, since the gate area is defined by etching crystal silicon, not by etching polycrystalline silicon. There is a low aspect ratio between the gate and the S/D, since the gate conductor and the source and drain conductors are aligned on same level. A suicide technique is applied to the source and drain for low parasitic resistance; however, this will not result in severe S/D junction leakage, since the source and drain conductors sit on the STI.

公开(公告)号：DE60101475T2

公开(公告)日：2004-11-25

申请号：DE60101475

申请日：2001-05-25

Applicant: IBM ,  INFINEON TECHNOLOGIES AG

Inventor： ELLIS WAYNE F ,  LI YUJUN ,  HSU L ,  WEINFURTNER OLIVER ,  JI L

IPC: G11C5/14 ,  G11C8/08 ,  G11C11/4074 ,  G11C11/4078

Abstract: Improved transistor array device performance is obtained by use of bias voltage regulation which tracks with a fraction of a monitor transistor threshold voltage. The circuitry and methods are especially useful for improving the performance of transistor array devices such as DRAM and embedded DRAM. These benefits are obtained especially when at least two bias voltages normally supplied to the array are regulated by tracking with a fraction of an actual threshold voltage of at least one monitor transistor. Performance improvements include improved reliability, wider operational bias conditions, reduced power consumption and (in the case of memory cells) improved retention time.